From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7E13AA0544; Mon, 10 Oct 2022 14:32:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0A1AA42BBB; Mon, 10 Oct 2022 14:31:49 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7961042BB0 for ; Mon, 10 Oct 2022 14:31:47 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29AC6iQk023773; Mon, 10 Oct 2022 05:31:47 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=U/KSMNc328myR2tcb7jbVwCQBTrmOYOYCjIMNQKduc4=; b=JL2TgNMVimECFxNuAftm83VRJZh3McJrfs1ky1mMWPCWcym2mMeAEblSEeXP8sgUTrhV lolm+Ci01kefdbO8cd290iLt0/0pdb9w0Y+abegjfluCEzb/f+Sjl/rQTMPW2gwnP6Pt 9rE4+muh1EzWQjX6DZlu+llLt5H/9uD2UU5ndVMt0o7RlVzvVaudTApGp/gmWnylOKXm FWjPeDNnTg4ks5J+eb19jGjmYNZ2jgQuiHOfsnhM+tjchOZnp0PnCci63SOm61JgKhsL c4MMHXobcxOVIU0Ybi5GAPLY4MZ+zNzubSSEIIOhFro0qreMH+swELQyvPP/0cScQaWy /A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3k40g4ts30-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 10 Oct 2022 05:31:46 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 10 Oct 2022 05:31:44 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 10 Oct 2022 05:31:44 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 9480D3F705A; Mon, 10 Oct 2022 05:31:42 -0700 (PDT) From: Volodymyr Fialko To: , Radu Nicolau , Akhil Goyal CC: , , , Volodymyr Fialko Subject: [PATCH v2 6/6] examples/ipsec-secgw: reduce number of QP for event lookaside Date: Mon, 10 Oct 2022 14:31:02 +0200 Message-ID: <20221010123102.3962719-7-vfialko@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010123102.3962719-1-vfialko@marvell.com> References: <20220804103626.102688-1-vfialko@marvell.com> <20221010123102.3962719-1-vfialko@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: 0Tm7OFqQ9bUxlkSS2GJ9w2IQ5EJtqWZJ X-Proofpoint-GUID: 0Tm7OFqQ9bUxlkSS2GJ9w2IQ5EJtqWZJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-10_06,2022-10-10_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Limit number of queue pairs to one for event lookaside mode, since all cores are using same queue in this mode. Signed-off-by: Volodymyr Fialko --- examples/ipsec-secgw/ipsec-secgw.c | 56 +++++++++++++++++++----------- 1 file changed, 36 insertions(+), 20 deletions(-) diff --git a/examples/ipsec-secgw/ipsec-secgw.c b/examples/ipsec-secgw/ipsec-secgw.c index 1d74aa60e5..e20bf50752 100644 --- a/examples/ipsec-secgw/ipsec-secgw.c +++ b/examples/ipsec-secgw/ipsec-secgw.c @@ -1540,7 +1540,7 @@ add_mapping(const char *str, uint16_t cdev_id, } static int32_t -add_cdev_mapping(struct rte_cryptodev_info *dev_info, uint16_t cdev_id, +add_cdev_mapping(const struct rte_cryptodev_info *dev_info, uint16_t cdev_id, uint16_t qp, struct lcore_params *params) { int32_t ret = 0; @@ -1596,6 +1596,37 @@ add_cdev_mapping(struct rte_cryptodev_info *dev_info, uint16_t cdev_id, return ret; } +static uint16_t +map_cdev_to_cores_from_config(enum eh_pkt_transfer_mode mode, int16_t cdev_id, + const struct rte_cryptodev_info *cdev_info, + uint16_t *last_used_lcore_id) +{ + uint16_t nb_qp = 0, i = 0, max_nb_qps; + + /* For event lookaside mode all sessions are bound to single qp. + * It's enough to bind one core, since all cores will share same qp + * Event inline mode do not use this functionality. + */ + if (mode == EH_PKT_TRANSFER_MODE_EVENT) { + add_cdev_mapping(cdev_info, cdev_id, nb_qp, &lcore_params[0]); + return 1; + } + + /* Check if there are enough queue pairs for all configured cores */ + max_nb_qps = RTE_MIN(nb_lcore_params, cdev_info->max_nb_queue_pairs); + + while (nb_qp < max_nb_qps && i < nb_lcore_params) { + if (add_cdev_mapping(cdev_info, cdev_id, nb_qp, + &lcore_params[*last_used_lcore_id])) + nb_qp++; + (*last_used_lcore_id)++; + *last_used_lcore_id %= nb_lcore_params; + i++; + } + + return nb_qp; +} + /* Check if the device is enabled by cryptodev_mask */ static int check_cryptodev_mask(uint8_t cdev_id) @@ -1607,13 +1638,13 @@ check_cryptodev_mask(uint8_t cdev_id) } static uint16_t -cryptodevs_init(uint16_t req_queue_num) +cryptodevs_init(enum eh_pkt_transfer_mode mode) { + struct rte_hash_parameters params = { 0 }; struct rte_cryptodev_config dev_conf; struct rte_cryptodev_qp_conf qp_conf; - uint16_t idx, max_nb_qps, qp, total_nb_qps, i; + uint16_t idx, qp, total_nb_qps; int16_t cdev_id; - struct rte_hash_parameters params = { 0 }; const uint64_t mseg_flag = multi_seg_required() ? RTE_CRYPTODEV_FF_IN_PLACE_SGL : 0; @@ -1654,23 +1685,8 @@ cryptodevs_init(uint16_t req_queue_num) cdev_id, rte_cryptodev_get_feature_name(mseg_flag)); - if (nb_lcore_params > cdev_info.max_nb_queue_pairs) - max_nb_qps = cdev_info.max_nb_queue_pairs; - else - max_nb_qps = nb_lcore_params; - - qp = 0; - i = 0; - while (qp < max_nb_qps && i < nb_lcore_params) { - if (add_cdev_mapping(&cdev_info, cdev_id, qp, - &lcore_params[idx])) - qp++; - idx++; - idx = idx % nb_lcore_params; - i++; - } - qp = RTE_MIN(max_nb_qps, RTE_MAX(req_queue_num, qp)); + qp = map_cdev_to_cores_from_config(mode, cdev_id, &cdev_info, &idx); if (qp == 0) continue; -- 2.25.1