From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F1731A0548; Tue, 11 Oct 2022 20:59:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 67ECE42BD8; Tue, 11 Oct 2022 20:57:40 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id D8FD942BBA for ; Tue, 11 Oct 2022 20:57:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665514649; x=1697050649; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TtG41x15hXAAO6scmbrplR1s1m+2/h2wY/aU7aoyF0Q=; b=XgoydPKSK+ImbOQ36dR3SUCjqWgkC3IuHEYtve4AoFKJUph5xwc+MAjz 4uCHeJ781XKLpGlFjv0L5onxRLocKEykTUNooEs9jUprUwOwHzGthblU3 TE1NoCbLUJSHswqdBNE8nC7/lfWQKsXR5npBdLjmwXnHGUZ+l8SL8m2hs aKesPEnunnVFX1tiwGtHb/mZqgioJqh/gpXfdujPrsSSQsLXWSleWZvVh 1kSkn/RAvq8xv2o7+GT/bVzvaLbQMwcybeMU5hEd/7GPtTAU1r2HRpU4e 214DaYc/uGw4Xgqzt2othxqbI/yIPN17Bnk99NtjDbcz3j57ofySl+Szx Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10497"; a="284981648" X-IronPort-AV: E=Sophos;i="5.95,177,1661842800"; d="scan'208";a="284981648" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2022 11:57:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10497"; a="604261564" X-IronPort-AV: E=Sophos;i="5.95,177,1661842800"; d="scan'208";a="604261564" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga006.jf.intel.com with ESMTP; 11 Oct 2022 11:57:28 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v3 17/30] baseband/acc100: add HARQ index helper function Date: Tue, 11 Oct 2022 19:53:33 -0700 Message-Id: <20221012025346.204394-18-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221012025346.204394-1-hernan.vargas@intel.com> References: <20221012025346.204394-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Refactor code to use the HARQ index helper function and make harq_idx uint32. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 29 +++++++++++---------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 9c1218e1f2..76667d1293 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1042,7 +1042,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, union acc_harq_layout_data *harq_layout) { uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset; - uint16_t harq_index; + uint32_t harq_index; uint32_t l; bool harq_prun = false; uint32_t max_hc_in; @@ -1090,8 +1090,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION); fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_LLR_COMPRESSION); - harq_index = op->ldpc_dec.harq_combined_output.offset / - ACC_HARQ_OFFSET; + harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset); #ifdef ACC100_EXT_MEM /* Limit cases when HARQ pruning is valid */ harq_prun = ((op->ldpc_dec.harq_combined_output.offset % @@ -1761,20 +1760,17 @@ acc100_dma_desc_ld_update(struct rte_bbdev_dec_op *op, *h_out_length = desc->data_ptrs[next_triplet].blen; next_triplet++; - if (check_bit(op->ldpc_dec.op_flags, - RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) { - desc->data_ptrs[next_triplet].address = - op->ldpc_dec.harq_combined_output.offset; + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) { + struct rte_bbdev_dec_op *prev_op; + uint32_t harq_idx, prev_harq_idx; + desc->data_ptrs[next_triplet].address = op->ldpc_dec.harq_combined_output.offset; /* Adjust based on previous operation */ - struct rte_bbdev_dec_op *prev_op = desc->op_addr; + prev_op = desc->op_addr; op->ldpc_dec.harq_combined_output.length = prev_op->ldpc_dec.harq_combined_output.length; - int16_t hq_idx = op->ldpc_dec.harq_combined_output.offset / - ACC_HARQ_OFFSET; - int16_t prev_hq_idx = - prev_op->ldpc_dec.harq_combined_output.offset - / ACC_HARQ_OFFSET; - harq_layout[hq_idx].val = harq_layout[prev_hq_idx].val; + harq_idx = hq_index(op->ldpc_dec.harq_combined_output.offset); + prev_harq_idx = hq_index(prev_op->ldpc_dec.harq_combined_output.offset); + harq_layout[harq_idx].val = harq_layout[prev_harq_idx].val; #ifndef ACC100_EXT_MEM struct rte_bbdev_op_data ho = op->ldpc_dec.harq_combined_output; @@ -2549,10 +2545,9 @@ harq_loopback(struct acc_queue *q, struct rte_bbdev_dec_op *op, bool ddr_mem_in = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE); union acc_harq_layout_data *harq_layout = q->d->harq_layout; - uint16_t harq_index = (ddr_mem_in ? + uint32_t harq_index = hq_index(ddr_mem_in ? op->ldpc_dec.harq_combined_input.offset : - op->ldpc_dec.harq_combined_output.offset) - / ACC_HARQ_OFFSET; + op->ldpc_dec.harq_combined_output.offset); uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs) & q->sw_ring_wrap_mask); -- 2.37.1