From: Hernan Vargas <hernan.vargas@intel.com>
To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,
maxime.coquelin@redhat.com
Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com,
Hernan Vargas <hernan.vargas@intel.com>
Subject: [PATCH v3 19/30] baseband/acc100: added LDPC transport block support
Date: Tue, 11 Oct 2022 19:53:35 -0700 [thread overview]
Message-ID: <20221012025346.204394-20-hernan.vargas@intel.com> (raw)
In-Reply-To: <20221012025346.204394-1-hernan.vargas@intel.com>
Added LDPC enqueue functions to handle transport blocks.
Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
---
drivers/baseband/acc/rte_acc100_pmd.c | 167 +++++++++++++++++++++++++-
1 file changed, 164 insertions(+), 3 deletions(-)
diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c
index 1ccbe4b8b7..1f671ac8f2 100644
--- a/drivers/baseband/acc/rte_acc100_pmd.c
+++ b/drivers/baseband/acc/rte_acc100_pmd.c
@@ -2152,6 +2152,56 @@ enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops,
return num;
}
+/* Enqueue one encode operations for ACC100 device for a partial TB
+ * all codes blocks have same configuration multiplexed on the same descriptor.
+ */
+static inline void
+enqueue_ldpc_enc_part_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op,
+ uint16_t total_enqueued_descs, int16_t num_cbs, uint32_t e,
+ uint16_t in_len_bytes, uint32_t out_len_bytes, uint32_t *in_offset,
+ uint32_t *out_offset)
+{
+ union acc_dma_desc *desc = NULL;
+ struct rte_mbuf *output_head, *output;
+ int i, next_triplet;
+ struct rte_bbdev_op_ldpc_enc *enc = &op->ldpc_enc;
+ uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_descs) & q->sw_ring_wrap_mask);
+
+ desc = q->ring_addr + desc_idx;
+ acc_fcw_le_fill(op, &desc->req.fcw_le, num_cbs, e);
+
+ /* This could be done at polling. */
+ acc_header_init(&desc->req);
+ desc->req.numCBs = num_cbs;
+
+ desc->req.m2dlen = 1 + num_cbs;
+ desc->req.d2mlen = num_cbs;
+ next_triplet = 1;
+
+ for (i = 0; i < num_cbs; i++) {
+ desc->req.data_ptrs[next_triplet].address =
+ rte_pktmbuf_iova_offset(enc->input.data, *in_offset);
+ *in_offset += in_len_bytes;
+ desc->req.data_ptrs[next_triplet].blen = in_len_bytes;
+ next_triplet++;
+ desc->req.data_ptrs[next_triplet].address =
+ rte_pktmbuf_iova_offset(enc->output.data, *out_offset);
+ *out_offset += out_len_bytes;
+ desc->req.data_ptrs[next_triplet].blen = out_len_bytes;
+ next_triplet++;
+ enc->output.length += out_len_bytes;
+ output_head = output = enc->output.data;
+ mbuf_append(output_head, output, out_len_bytes);
+ }
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+ rte_memdump(stderr, "FCW", &desc->req.fcw_le,
+ sizeof(desc->req.fcw_le) - 8);
+ rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc));
+#endif
+
+}
+
/* Enqueue one encode operations for ACC100 device in CB mode */
static inline int
enqueue_ldpc_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op *op,
@@ -2296,6 +2346,76 @@ enqueue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op,
return current_enqueued_cbs;
}
+/* Enqueue one encode operations for ACC100 device in TB mode.
+ * returns the number of descs used.
+ */
+static inline int
+enqueue_ldpc_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op,
+ uint16_t enq_descs, uint8_t cbs_in_tb)
+{
+#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE
+ if (validate_ldpc_enc_op(op, q) == -1) {
+ rte_bbdev_log(ERR, "LDPC encoder validation failed");
+ return -EINVAL;
+ }
+#endif
+ uint8_t num_a, num_b;
+ uint16_t desc_idx;
+ uint8_t r = op->ldpc_enc.tb_params.r;
+ uint8_t cab = op->ldpc_enc.tb_params.cab;
+ union acc_dma_desc *desc;
+ uint16_t init_enq_descs = enq_descs;
+ uint16_t input_len_B = ((op->ldpc_enc.basegraph == 1 ? 22 : 10) *
+ op->ldpc_enc.z_c - op->ldpc_enc.n_filler) >> 3;
+ uint32_t in_offset = 0, out_offset = 0;
+ uint16_t return_descs;
+
+ if (check_bit(op->ldpc_enc.op_flags, RTE_BBDEV_LDPC_CRC_24B_ATTACH))
+ input_len_B -= 3;
+
+ if (r < cab) {
+ num_a = cab - r;
+ num_b = cbs_in_tb - cab;
+ } else {
+ num_a = 0;
+ num_b = cbs_in_tb - r;
+ }
+
+ while (num_a > 0) {
+ uint32_t e = op->ldpc_enc.tb_params.ea;
+ uint32_t out_len_bytes = (e + 7) >> 3;
+ uint8_t enq = RTE_MIN(num_a, ACC_MUX_5GDL_DESC);
+ num_a -= enq;
+ enqueue_ldpc_enc_part_tb(q, op, enq_descs, enq, e, input_len_B,
+ out_len_bytes, &in_offset, &out_offset);
+ enq_descs++;
+ }
+ while (num_b > 0) {
+ uint32_t e = op->ldpc_enc.tb_params.eb;
+ uint32_t out_len_bytes = (e + 7) >> 3;
+ uint8_t enq = RTE_MIN(num_b, ACC_MUX_5GDL_DESC);
+ num_b -= enq;
+ enqueue_ldpc_enc_part_tb(q, op, enq_descs, enq, e, input_len_B,
+ out_len_bytes, &in_offset, &out_offset);
+ enq_descs++;
+ }
+
+ return_descs = enq_descs - init_enq_descs;
+ /* Keep total number of CBs in first TB. */
+ desc_idx = ((q->sw_ring_head + init_enq_descs) & q->sw_ring_wrap_mask);
+ desc = q->ring_addr + desc_idx;
+ desc->req.cbs_in_tb = return_descs; /** Actual number of descriptors. */
+ desc->req.op_addr = op;
+
+ /* Set SDone on last CB descriptor for TB mode. */
+ desc_idx = ((q->sw_ring_head + enq_descs - 1) & q->sw_ring_wrap_mask);
+ desc = q->ring_addr + desc_idx;
+ desc->req.sdone_enable = 1;
+ desc->req.irq_enable = q->irq_enable;
+ desc->req.op_addr = op;
+ return return_descs;
+}
+
#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE
/* Validates turbo decoder parameters */
static inline int
@@ -2876,7 +2996,10 @@ enqueue_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op,
uint16_t current_enqueued_cbs = 0;
#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE
- /* Validate op structure */
+ if (cbs_in_tb == 0) {
+ rte_bbdev_log(ERR, "Turbo decoder invalid number of CBs");
+ return -EINVAL;
+ }
if (validate_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo decoder validation rejected");
return -EINVAL;
@@ -3102,7 +3225,45 @@ acc100_enqueue_enc_tb(struct rte_bbdev_queue_data *q_data,
return i;
}
-/* Check room in AQ for the enqueues batches into Qmgr */
+/* Enqueue LDPC encode operations for ACC100 device in TB mode. */
+static uint16_t
+acc100_enqueue_ldpc_enc_tb(struct rte_bbdev_queue_data *q_data,
+ struct rte_bbdev_enc_op **ops, uint16_t num)
+{
+ struct acc_queue *q = q_data->queue_private;
+ int32_t avail = acc_ring_avail_enq(q);
+ uint16_t i, enqueued_descs = 0;
+ uint8_t cbs_in_tb;
+ int descs_used;
+
+ for (i = 0; i < num; ++i) {
+ cbs_in_tb = get_num_cbs_in_tb_ldpc_enc(&ops[i]->ldpc_enc);
+ /* Check if there are available space for further processing. */
+ if (unlikely(avail - cbs_in_tb < 0)) {
+ acc_enqueue_ring_full(q_data);
+ break;
+ }
+ descs_used = enqueue_ldpc_enc_one_op_tb(q, ops[i], enqueued_descs, cbs_in_tb);
+ if (descs_used < 0) {
+ acc_enqueue_invalid(q_data);
+ break;
+ }
+ enqueued_descs += descs_used;
+ avail -= descs_used;
+ }
+ if (unlikely(enqueued_descs == 0))
+ return 0; /* Nothing to enqueue. */
+
+ acc_dma_enqueue(q, enqueued_descs, &q_data->queue_stats);
+
+ /* Update stats. */
+ q_data->queue_stats.enqueued_count += i;
+ q_data->queue_stats.enqueue_err_count += num - i;
+
+ return i;
+}
+
+/* Check room in AQ for the enqueues batches into Qmgr. */
static int32_t
acc100_aq_avail(struct rte_bbdev_queue_data *q_data, uint16_t num_ops)
{
@@ -3139,7 +3300,7 @@ acc100_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
if (unlikely((aq_avail <= 0) || (num == 0)))
return 0;
if (ops[0]->ldpc_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
- return acc100_enqueue_enc_tb(q_data, ops, num);
+ return acc100_enqueue_ldpc_enc_tb(q_data, ops, num);
else
return acc100_enqueue_ldpc_enc_cb(q_data, ops, num);
}
--
2.37.1
next prev parent reply other threads:[~2022-10-11 18:59 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-12 2:53 [PATCH v3 00/30] baseband/acc100: changes for 22.11 Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 01/30] baseband/acc100: fix ring availability calculation Hernan Vargas
2022-10-14 9:18 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 02/30] baseband/acc100: add function to check AQ availability Hernan Vargas
2022-10-14 9:25 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 03/30] baseband/acc100: memory leak fix Hernan Vargas
2022-10-14 9:29 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 04/30] baseband/acc100: add LDPC encoder padding function Hernan Vargas
2022-10-14 9:33 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 05/30] baseband/acc100: check turbo dec/enc input Hernan Vargas
2022-10-14 9:35 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 06/30] baseband/acc100: check for unlikely operation vals Hernan Vargas
2022-10-14 9:39 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 07/30] baseband/acc100: enforce additional check on FCW Hernan Vargas
2022-10-14 9:48 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 08/30] baseband/acc100: allocate ring/queue mem when NULL Hernan Vargas
2022-10-14 9:55 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 09/30] baseband/acc100: reduce input length for CRC24B Hernan Vargas
2022-10-14 9:56 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 10/30] baseband/acc100: fix clearing PF IR outside handler Hernan Vargas
2022-10-14 9:56 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 11/30] baseband/acc100: set device min alignment to 1 Hernan Vargas
2022-10-14 10:02 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 12/30] baseband/acc100: add protection for NULL HARQ input Hernan Vargas
2022-10-14 10:03 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 13/30] baseband/acc100: reset pointer after rte_free Hernan Vargas
2022-10-14 10:03 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 14/30] baseband/acc100: fix debug print for LDPC FCW Hernan Vargas
2022-10-14 10:03 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 15/30] baseband/acc100: add enqueue status Hernan Vargas
2022-10-14 10:04 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 16/30] baseband/acc100: add scatter-gather support Hernan Vargas
2022-10-14 10:06 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 17/30] baseband/acc100: add HARQ index helper function Hernan Vargas
2022-10-14 10:06 ` Maxime Coquelin
2022-10-12 2:53 ` [PATCH v3 18/30] baseband/acc100: enable input validation by default Hernan Vargas
2022-10-13 12:56 ` [EXT] " Akhil Goyal
2022-10-18 16:28 ` Maxime Coquelin
2022-10-19 22:12 ` Chautru, Nicolas
2022-10-21 8:06 ` Maxime Coquelin
2022-10-12 2:53 ` Hernan Vargas [this message]
2022-10-12 2:53 ` [PATCH v3 20/30] baseband/acc100: update validate LDPC enc/dec Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 21/30] baseband/acc100: implement configurable queue depth Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 22/30] baseband/acc100: add queue stop operation Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 23/30] baseband/acc100: update uplink CB input length Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 24/30] baseband/acc100: rename ldpc encode function arg Hernan Vargas
2022-10-13 13:04 ` [EXT] " Akhil Goyal
2022-10-12 2:53 ` [PATCH v3 25/30] baseband/acc100: update log messages Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 26/30] baseband/acc100: store FCW from first CB descriptor Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 27/30] baseband/acc100: update device info Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 28/30] baseband/acc100: add ring companion address Hernan Vargas
2022-10-12 2:53 ` [PATCH v3 29/30] baseband/acc100: add workaround for deRM corner cases Hernan Vargas
2022-10-13 13:09 ` [EXT] " Akhil Goyal
2022-10-12 2:53 ` [PATCH v3 30/30] baseband/acc100: configure PMON control registers Hernan Vargas
2022-10-13 8:28 ` [EXT] [PATCH v3 00/30] baseband/acc100: changes for 22.11 Akhil Goyal
2022-10-13 13:01 ` Akhil Goyal
2022-10-14 2:46 ` Chautru, Nicolas
2022-10-14 6:33 ` Akhil Goyal
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