From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 271D8A00C2; Fri, 14 Oct 2022 07:43:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CAAA442C15; Fri, 14 Oct 2022 07:43:33 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id BC18042C28 for ; Fri, 14 Oct 2022 07:43:32 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29E2JPJo005899 for ; Thu, 13 Oct 2022 22:43:32 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Awd1Qngf81AUIaIwPv4cjhmH6PL3+wZOhndRiRRS0c0=; b=BC8sL3EAmNZmE00vIJ9xQCPudgJjhcZRc8a5IlT7bjpSc2MkqBVYu4s5F/RpXjlkr4iN WsBCx6xA86tnmNP1hpw5nC4ShQkw+71ELgqqwssyQcPE/2I0SqZ+Z4+k4zIdo7Fcthf4 i35claL+6ToXPj/VhG+1Veq3tl1GMJ7+wlrgKLr3HXLvoxTeZ+22Nbt/Do+ztV72xruf wyRgq/gKPCIPhi90k5+79OzQaP9mSP40iyP7WcSQy522cBcBgyr6G2tZdJ/MJfIiQw+y 2teTpib/GaGhi+uv/PlqBxuWUvlurtgbaMcKKgBjZB8/umlrRdnfjHP1DtNi5cYeS1Jb eQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3k6xvp0k6h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 13 Oct 2022 22:43:31 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 13 Oct 2022 22:43:30 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 13 Oct 2022 22:43:30 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id B63423F7058; Thu, 13 Oct 2022 22:43:27 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Pavan Nikhilesh , "Shijith Thotton" CC: , Subject: [PATCH v3 04/13] net/cnxk: use NIX Tx offset for cn10kb Date: Fri, 14 Oct 2022 11:13:08 +0530 Message-ID: <20221014054317.1151306-4-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014054317.1151306-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> <20221014054317.1151306-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: LKXVcK_t5bxZHTLD67tsR-d5eiceI8bx X-Proofpoint-GUID: LKXVcK_t5bxZHTLD67tsR-d5eiceI8bx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_02,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In outbound inline case, use NIX Tx offset instead of NIX Tx address for CN103XX as per new instruction format. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_constants.h | 1 + drivers/event/cnxk/cn10k_worker.h | 3 +++ drivers/net/cnxk/cn10k_ethdev.c | 6 ++++++ drivers/net/cnxk/cn10k_ethdev.h | 3 ++- drivers/net/cnxk/cn10k_ethdev_sec.c | 2 ++ drivers/net/cnxk/cn10k_tx.h | 4 ++-- 6 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h index c693dde62e..0495965daa 100644 --- a/drivers/common/cnxk/roc_constants.h +++ b/drivers/common/cnxk/roc_constants.h @@ -12,6 +12,7 @@ /* [CN10K, .) */ #define ROC_LMT_LINE_SZ 128 #define ROC_NUM_LMT_LINES 2048 +#define ROC_LMT_LINES_PER_STR_LOG2 4 #define ROC_LMT_LINES_PER_CORE_LOG2 5 #define ROC_LMT_LINE_SIZE_LOG2 7 #define ROC_LMT_BASE_PER_CORE_LOG2 \ diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h index 7a82dd352a..75a2ff244a 100644 --- a/drivers/event/cnxk/cn10k_worker.h +++ b/drivers/event/cnxk/cn10k_worker.h @@ -595,6 +595,9 @@ cn10k_sso_tx_one(struct cn10k_sso_hws *ws, struct rte_mbuf *m, uint64_t *cmd, ws->gw_rdata = roc_sso_hws_head_wait(ws->base); cn10k_sso_txq_fc_wait(txq); + if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec) + cn10k_nix_sec_fc_wait_one(txq); + roc_lmt_submit_steorl(lmt_id, pa); if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) { diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index 0b33b3a496..4658713591 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -538,6 +538,9 @@ cn10k_nix_reassembly_capability_get(struct rte_eth_dev *eth_dev, int rc = -ENOTSUP; RTE_SET_USED(eth_dev); + if (!roc_nix_has_reass_support(&dev->nix)) + return -ENOTSUP; + if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) { reassembly_capa->timeout_ms = 60 * 1000; reassembly_capa->max_frags = 4; @@ -565,6 +568,9 @@ cn10k_nix_reassembly_conf_set(struct rte_eth_dev *eth_dev, struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); int rc = 0; + if (!roc_nix_has_reass_support(&dev->nix)) + return -ENOTSUP; + if (!conf->flags) { /* Clear offload flags on disable */ dev->rx_offload_flags &= ~NIX_RX_REAS_F; diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h index d0a5b136e3..948c8348ad 100644 --- a/drivers/net/cnxk/cn10k_ethdev.h +++ b/drivers/net/cnxk/cn10k_ethdev.h @@ -75,7 +75,8 @@ struct cn10k_sec_sess_priv { uint16_t partial_len : 10; uint16_t chksum : 2; uint16_t dec_ttl : 1; - uint16_t rsvd : 3; + uint16_t nixtx_off : 1; + uint16_t rsvd : 2; }; uint64_t u64; diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 6de4a284da..3ca707f038 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -798,6 +798,8 @@ cn10k_eth_sec_session_create(void *device, sess_priv.chksum = (!ipsec->options.ip_csum_enable << 1 | !ipsec->options.l4_csum_enable); sess_priv.dec_ttl = ipsec->options.dec_ttl; + if (roc_model_is_cn10kb_a0()) + sess_priv.nixtx_off = 1; /* Pointer from eth_sec -> outb_sa */ eth_sec->sa = outb_sa; diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index 36fa96f83f..d375183f90 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -397,7 +397,7 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1, /* DLEN passed is excluding L2 HDR */ pkt_len -= l2_len; } - w0 |= nixtx; + w0 |= sess_priv.nixtx_off ? ((((int64_t)nixtx - (int64_t)dptr) & 0xFFFFF) << 32) : nixtx; /* CPT word 0 and 1 */ cmd01 = vdupq_n_u64(0); cmd01 = vsetq_lane_u64(w0, cmd01, 0); @@ -539,7 +539,7 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr, sg->seg1_size = pkt_len + dlen_adj; pkt_len -= l2_len; } - w0 |= nixtx; + w0 |= sess_priv.nixtx_off ? ((((int64_t)nixtx - (int64_t)dptr) & 0xFFFFF) << 32) : nixtx; /* CPT word 0 and 1 */ cmd01 = vdupq_n_u64(0); cmd01 = vsetq_lane_u64(w0, cmd01, 0); -- 2.25.1