From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C98EBA06CC; Wed, 19 Oct 2022 16:43:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9364B42BF5; Wed, 19 Oct 2022 16:43:43 +0200 (CEST) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2067.outbound.protection.outlook.com [40.107.244.67]) by mails.dpdk.org (Postfix) with ESMTP id C776542BB1 for ; Wed, 19 Oct 2022 16:43:40 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ELRoMUHvLCmNcf7StpkMncMhEzWQVV2GhGWuyZEvPGMhmfnFmr86zEmqc5kTCbBLFjiPib2KuUkDWnB6pw0SjdbraV4j8I0zedNDkQioMbkptvDb4gzoY3ys3bkqOeF69WJDSEopoXQjapoLi2I+Y05bmPX8TIIoe9ybykhfHAlnXvHYuFwAvUef/siQL+Go2boo6oZ68ITCKpb4fGVQDH49+Bjv4F4PgDKQLIjK2LMILfxvBeUX5l1kWVkoeLcfPw0Bq4mP36w8Sb3tg00ma6a4424meSHlM1VcXI13SKIulwfECtnx8Fx0YBYuu64hY7VIW6WmXRfXdo0Q5q64uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hsAe0vcrL07SUXCFz5bgbQnq3pFv3FXFrIewr8YWOU8=; b=bp5M2jNutLXYrnL6Slc7frX9JNtNM4WjZgtvyM/8VpfElHCFNMZMVKLBwcnHdRw6mcNwycsrr3hkgaKOBQM0vwFuPW1hmcSw/O7dYjB7VwW2LLTlYf5vpm1mxy4ab/Phrj+Z1LI+MFTP14GwGIauv9xlcXD860xGVHS7LWjoe9AXSeKAG4Tn8bqkuWLSgO6wYKUqRy1DBmERyeegyPer0OizxfWRSQDJjClujKDuNq5y+G34Wq+B9h0QaBuzROjzcWU6vC4fW0Q0q5slK8b9pEIxndZ0VUVl36NoSj3Dmi0MMv4E5HcOKtoNfj2YT0In03SZNAY98JbMzJ29TsDUuw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none (sender ip is 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=fail (p=reject sp=reject pct=100) action=oreject header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hsAe0vcrL07SUXCFz5bgbQnq3pFv3FXFrIewr8YWOU8=; b=f9siefJTvb0A5znI8/CTRAQn7eLcII9jt6EDoemUPHda/Jkfstnc3iHLGWDNmp9NB3RhXJ22GAZnjB4/ElmPaiadB6JN0QsSuGBIUIfdJT6eOkHs5H5TtUBbknuRasAXIIxtZ+P8mmxpCyR152EZlRCBp4Z9+6vZ4IgbJnEPHc6HjX/k9WL6/WfFak2re3gkvseQ5VeoD3SJPRlylCiSvP7AXDISoxLAOBnX/BCp0AAYUhMDKIPgsoeSC6b/vAttQV784aCcNK5vrO7NUyO3vpxRLWHVA+Sxi4N/3SWTKrpJ1AH/4nJTijuB6v1zEL9VivKyvU1CvtdOCWAy1H4lmg== Received: from BN0PR04CA0194.namprd04.prod.outlook.com (2603:10b6:408:e9::19) by DS7PR12MB5765.namprd12.prod.outlook.com (2603:10b6:8:74::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.33; Wed, 19 Oct 2022 14:43:38 +0000 Received: from BN8NAM11FT048.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e9:cafe::cd) by BN0PR04CA0194.outlook.office365.com (2603:10b6:408:e9::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.34 via Frontend Transport; Wed, 19 Oct 2022 14:43:38 +0000 X-MS-Exchange-Authentication-Results: spf=none (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=fail action=oreject header.from=nvidia.com; Received-SPF: None (protection.outlook.com: nvidia.com does not designate permitted sender hosts) Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT048.mail.protection.outlook.com (10.13.177.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.16 via Frontend Transport; Wed, 19 Oct 2022 14:43:38 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Wed, 19 Oct 2022 07:43:27 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 19 Oct 2022 07:43:24 -0700 From: Alex Vesker To: , , , , Matan Azrad CC: , , Dariusz Sosnowski Subject: [v4 04/18] net/mlx5: add port to metadata conversion Date: Wed, 19 Oct 2022 17:42:44 +0300 Message-ID: <20221019144258.16282-5-valex@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221019144258.16282-1-valex@nvidia.com> References: <20220922190345.394-1-valex@nvidia.com> <20221019144258.16282-1-valex@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT048:EE_|DS7PR12MB5765:EE_ X-MS-Office365-Filtering-Correlation-Id: e9cf5d8d-a52a-4127-27c1-08dab1e04f4f X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xut49ru9V4E06mgDJj260lD+8zX778jJDiIIyONqQQTQlnijsEqKh2wHoEdIq9i6X3qPxzX2E7Wnj5RobGFj7UjdlCGK0ayKeHkr0GAfbFXHDB/Es74n5h4PrzXwiDHj2l32i+x2QW4g0MCnVQOlN56eucv/RGCr6dUoslmAy0uEafW4YvSmXRYAYB6ANUN+A6PKkFyieVrumfaUgPBSevujEB11HDg3aGlGToS+2J8AT1WpGiATJZSeHmaYbnDKYISLkBlwke+0Rv513HyHrI9bkAxmvD6sRqFivbeeTgFkwDJfhasFzl6y5ziOjnYuaEF+WhEfNY4n6Iw01l7/OFvFshdPRgYPkU1JGjFm5V+MyXhFQ49zq9z41+FBScvKZQnuXbuTk04wsBNiMPzgGkuzl4V7d5w9x3f0GZcV5bZIcuWiBnXKwdA0pfuN/ZCTUNtl+NTImwSLGwOYb9OZY8sJMNsVC+aKkfegNciVzHBqU7CKiVtjz8jUmRW1m7zpofYCd3bVjR3bX/wBe+zsa2seogk5WiZdE3e6W+i8EcIIzW5TMpxM6W3EIkSAnGwby8Ay9jcDS3AgkLuZe+jwjF0o4Rp7R0KZLGnUgDIKrz121qiNk2OwzlZtxP3m0jxOObHs7e7pSYtKK/JVnJIq061EKlqxhkwrz8eHI6Efr9EXfGKKtgHWiZJNs/BoaKkZxCQ9PYbQHCyrwg8fHxBTfXrzx/nqYludjsMlyNMTUCCaTIrGpAMTL7uRXh5VVTtUXzDQ+Bjf6GfPCY9zuWcTJVr0pTYsRkZt/PWeNnneMY4tFBXIaeaN/HkV6604niyl X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(396003)(376002)(39860400002)(346002)(136003)(451199015)(46966006)(36840700001)(40470700004)(356005)(36860700001)(82740400003)(7636003)(6636002)(110136005)(5660300002)(86362001)(8676002)(70586007)(70206006)(4326008)(316002)(54906003)(40460700003)(8936002)(2616005)(426003)(2906002)(47076005)(82310400005)(1076003)(16526019)(186003)(83380400001)(336012)(478600001)(6666004)(107886003)(41300700001)(26005)(6286002)(7696005)(40480700001)(55016003)(36756003)(21314003)(309714004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2022 14:43:38.5537 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9cf5d8d-a52a-4127-27c1-08dab1e04f4f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5765 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dariusz Sosnowski This patch initial version of functions used to: - convert between ethdev port_id and internal tag/mask value, - convert between IB context and internal tag/mask value. Signed-off-by: Dariusz Sosnowski --- drivers/net/mlx5/linux/mlx5_os.c | 10 +++++- drivers/net/mlx5/mlx5.c | 1 + drivers/net/mlx5/mlx5_flow.c | 6 ++++ drivers/net/mlx5/mlx5_flow.h | 52 ++++++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5_flow_hw.c | 29 ++++++++++++++++++ 5 files changed, 97 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 60677eb8d7..98c6374547 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1541,8 +1541,16 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, if (!priv->hrxqs) goto error; rte_rwlock_init(&priv->ind_tbls_lock); - if (priv->sh->config.dv_flow_en == 2) + if (priv->sh->config.dv_flow_en == 2) { +#ifdef HAVE_IBV_FLOW_DV_SUPPORT + if (priv->vport_meta_mask) + flow_hw_set_port_info(eth_dev); return eth_dev; +#else + DRV_LOG(ERR, "DV support is missing for HWS."); + goto error; +#endif + } /* Port representor shares the same max priority with pf port. */ if (!priv->sh->flow_priority_check_flag) { /* Supported Verbs flow priority number detection. */ diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 752b60d769..1d10932619 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1944,6 +1944,7 @@ mlx5_dev_close(struct rte_eth_dev *dev) mlx5_flex_item_port_cleanup(dev); #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) flow_hw_resource_release(dev); + flow_hw_clear_port_info(dev); #endif if (priv->rxq_privs != NULL) { /* XXX race condition if mlx5_rx_burst() is still running. */ diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 742dbd6358..9d94da0868 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -33,6 +33,12 @@ #include "mlx5_common_os.h" #include "rte_pmd_mlx5.h" +/* + * Shared array for quick translation between port_id and vport mask/values + * used for HWS rules. + */ +struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS]; + struct tunnel_default_miss_ctx { uint16_t *queue; __extension__ diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 288e09d5ba..17102623c1 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1323,6 +1323,58 @@ struct mlx5_flow_split_info { uint64_t prefix_layers; /**< Prefix subflow layers. */ }; +struct flow_hw_port_info { + uint32_t regc_mask; + uint32_t regc_value; + uint32_t is_wire:1; +}; + +extern struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS]; + +/* + * Get metadata match tag and mask for given rte_eth_dev port. + * Used in HWS rule creation. + */ +static __rte_always_inline const struct flow_hw_port_info * +flow_hw_conv_port_id(const uint16_t port_id) +{ + struct flow_hw_port_info *port_info; + + if (port_id >= RTE_MAX_ETHPORTS) + return NULL; + port_info = &mlx5_flow_hw_port_infos[port_id]; + return !!port_info->regc_mask ? port_info : NULL; +} + +#ifdef HAVE_IBV_FLOW_DV_SUPPORT +/* + * Get metadata match tag and mask for the uplink port represented + * by given IB context. Used in HWS context creation. + */ +static __rte_always_inline const struct flow_hw_port_info * +flow_hw_get_wire_port(struct ibv_context *ibctx) +{ + struct ibv_device *ibdev = ibctx->device; + uint16_t port_id; + + MLX5_ETH_FOREACH_DEV(port_id, NULL) { + const struct mlx5_priv *priv = + rte_eth_devices[port_id].data->dev_private; + + if (priv && priv->master) { + struct ibv_context *port_ibctx = priv->sh->cdev->ctx; + + if (port_ibctx->device == ibdev) + return flow_hw_conv_port_id(port_id); + } + } + return NULL; +} +#endif + +void flow_hw_set_port_info(struct rte_eth_dev *dev); +void flow_hw_clear_port_info(struct rte_eth_dev *dev); + typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, const struct rte_flow_item items[], diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 12498794a5..fe809a83b9 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -2208,6 +2208,35 @@ flow_hw_resource_release(struct rte_eth_dev *dev) priv->nb_queue = 0; } +/* Sets vport tag and mask, for given port, used in HWS rules. */ +void +flow_hw_set_port_info(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + uint16_t port_id = dev->data->port_id; + struct flow_hw_port_info *info; + + MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS); + info = &mlx5_flow_hw_port_infos[port_id]; + info->regc_mask = priv->vport_meta_mask; + info->regc_value = priv->vport_meta_tag; + info->is_wire = priv->master; +} + +/* Clears vport tag and mask used for HWS rules. */ +void +flow_hw_clear_port_info(struct rte_eth_dev *dev) +{ + uint16_t port_id = dev->data->port_id; + struct flow_hw_port_info *info; + + MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS); + info = &mlx5_flow_hw_port_infos[port_id]; + info->regc_mask = 0; + info->regc_value = 0; + info->is_wire = 0; +} + /** * Create shared action. * -- 2.18.1