From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 82FB3A09F2; Wed, 19 Oct 2022 22:58:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7600242C4A; Wed, 19 Oct 2022 22:58:10 +0200 (CEST) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) by mails.dpdk.org (Postfix) with ESMTP id 5743042C4A for ; Wed, 19 Oct 2022 22:58:09 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HBthse/pAEkSvBC74RcWUnmNZlzCtqd17PJe2eF8PmgUOTuBh1WlKK5bl95XiXu+Gyzmq6n4LEt7ELi8G/JPus4y7S1WoZM9czRac2eMtpZet+Pd/lTyeuj2dq0W8CwpiNlswzJWkvadq7IGDEpFj3jjcHjdw2U36VD1mkLWDLh8aEBXFJOkdOGxsNVWYxEfU+ff+sM2TN89aLongsj72Mqn4Pl44kuxmnsk/E8Ft3/EvX+5zb7DcCna6LFLlVwNfSw+xPnLm2X6DNZl5kmr3OxF19lq5gCjkM5ImD8TY5bWNRJmHkjPR94LEknUkylBfefqrCL1AtePfq9X7l7Vvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=P6YPqGsmLvUPm8AbOHwD51VmCPEC60NjyRHq+Fzx7o8=; b=RyxoSpiURc/D0uJ8A7F3LAiLR19uK+aCgbTYL9BuNPNo47iWoiC8u40+R1YmqBflRVmfnZXIUSFvJVYfjQI5zM1ej3cLmSVMAL6Mj5WYhHj0WDWe5iHs3YknW/A6a9CjIoTIPO3teGxPK0lp0E5wJgw+n2kGzXDYF7+H/cF2nboVUlMy45kfNks0UDHtyHgXJlgJdt4sHd81PPUTt/Ik923S5+11Mvy1TCwChzP1iueRqOWALUWFdL68gg2M4zX7/kMZGkHyJ2c6edRp0ywFQXtG5+3TjR9dmLkWLYHWygYF4FqJgQpPtbpqpLCyeypMJ91q60Fhs6DJXHtpscN8CA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none (sender ip is 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=fail (p=reject sp=reject pct=100) action=oreject header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=P6YPqGsmLvUPm8AbOHwD51VmCPEC60NjyRHq+Fzx7o8=; b=cATOFkiZNymRY73jBJfZ/csqRD5dUvsK/83B9aS5ce2zGv1w60Js3mDuZsWd838rizOEryiqVbU9RQAvkm4neMRu/8gu6wwp1lBoy//3RFNRete/PtZXbndEsgoY41IB0u+uMBBuX8+nRjXVkup0ZHq4KkHGMYA9zZhPvP5CJblUl+SIPf42G9ewFU3niarZz5Vk8P3pA/KmiquILiEEEax93A0hSD2hxh+kiNVNykiw/2iLPqhC5DX9zzE8AWvfhnus3kd5H0g92VIlbNdQ8RRCHuCikWDPrxDRP35w99Z3yUD62ReKN5MH/gk7tdcOjHbNw4wXmYGsNdjCBNArxA== Received: from DS7PR03CA0154.namprd03.prod.outlook.com (2603:10b6:5:3b2::9) by BY5PR12MB4998.namprd12.prod.outlook.com (2603:10b6:a03:1d4::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.32; Wed, 19 Oct 2022 20:58:07 +0000 Received: from DM6NAM11FT012.eop-nam11.prod.protection.outlook.com (2603:10b6:5:3b2:cafe::9f) by DS7PR03CA0154.outlook.office365.com (2603:10b6:5:3b2::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.32 via Frontend Transport; Wed, 19 Oct 2022 20:58:07 +0000 X-MS-Exchange-Authentication-Results: spf=none (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=fail action=oreject header.from=nvidia.com; Received-SPF: None (protection.outlook.com: nvidia.com does not designate permitted sender hosts) Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT012.mail.protection.outlook.com (10.13.173.109) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.16 via Frontend Transport; Wed, 19 Oct 2022 20:58:07 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Wed, 19 Oct 2022 13:57:49 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 19 Oct 2022 13:57:46 -0700 From: Alex Vesker To: , , , , Matan Azrad CC: , , Bing Zhao Subject: [v5 05/18] common/mlx5: query set capability of registers Date: Wed, 19 Oct 2022 23:57:08 +0300 Message-ID: <20221019205721.8077-6-valex@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221019205721.8077-1-valex@nvidia.com> References: <20220922190345.394-1-valex@nvidia.com> <20221019205721.8077-1-valex@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT012:EE_|BY5PR12MB4998:EE_ X-MS-Office365-Filtering-Correlation-Id: 6f73336a-f04a-41d7-de8d-08dab2149fb1 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BU+ZuBQVsk5V7zDsotE9ZKJXDJ4rBD2tgjwZtz6ags9qUUhfVP/NE3VsCSd+GNBhXI9Ldu0LW7rR8wBMNLjIJNoV35jfRVrv+4JD1ijropkdSpyCI/bS5ufLTLv/Ok4Xj7Nqr4z7bhKv/vAdrX0wcxlp3vkDAzutXMtknFSllr7s81mWgDHUcOMsfd9t7+CCYrsc4h6ZBu7z5NKmacP8SPaDZzWHLF8eUd7tU3ma0MryW9IBihj9jZdnXWRFaYqKucA3qdC9dEos0MFztbKq2O6HBRM9XsXA55AFkWVRif+43TtB6OU8ZI3dYlTvE85DwR/EDS7CTuhBQymv+Cufn6mZ5o8Drd4By+mNUnmnz5GJPhe/urEn9ctp6gyE1hz3aIBbgbg0HrIuZBPzeIsjWO7o+1M61IVKroF6EenxEaW2v+Pee2aBgchtRu7ka0zIp012HlYyUkQg5yV7AWs9xfaScaQ/zJnlY+r9rZqCNjjTH4PwjzCkpADKvjlYT3yzpDNaiDneUHqWHjDNARMa3eBvC8ZuB5H9V/kinjE3L8+jbqHaLxSYEGHysh7g7RYrhcYLywl2LOPU+KxTDLFpoywt0N3BEnfZ35VDmiXfgR7AHxkctjWo09htckpsCwjjlfHc5hbrGA8uJkqAAtusPlrOtXE0VhJOsyI2wqi0g/7Sn9XKPyO9Y2Lnq+SqOXVXEuXNiwar9rVwJlEm25MxZT4fzQCYAJMo5yIelp8bJXuGqlmNaO4tq04t8ZnEocBG17lJ4JIb/jD2/v+j2tRb3Q== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(346002)(136003)(376002)(396003)(39860400002)(451199015)(36840700001)(40470700004)(46966006)(110136005)(5660300002)(70586007)(6636002)(316002)(54906003)(70206006)(7696005)(478600001)(8676002)(41300700001)(4326008)(26005)(6286002)(16526019)(1076003)(2906002)(336012)(8936002)(186003)(2616005)(83380400001)(82740400003)(36756003)(356005)(7636003)(82310400005)(426003)(47076005)(107886003)(6666004)(36860700001)(55016003)(40480700001)(40460700003)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2022 20:58:07.3108 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6f73336a-f04a-41d7-de8d-08dab2149fb1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4998 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Bing Zhao In the flow table capabilities, new fields are added to query the capability to set, add, copy to a REG_C_x. The set capability are queried and saved for the future usage. Signed-off-by: Bing Zhao --- drivers/common/mlx5/mlx5_devx_cmds.c | 30 +++++++++++++++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++ drivers/common/mlx5/mlx5_prm.h | 45 +++++++++++++++++++++++++--- 3 files changed, 73 insertions(+), 4 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 76f0b6724f..9c185366d0 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -1064,6 +1064,24 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->modify_outer_ip_ecn = MLX5_GET (flow_table_nic_cap, hcattr, ft_header_modify_nic_receive.outer_ip_ecn); + attr->set_reg_c = 0xff; + if (attr->nic_flow_table) { +#define GET_RX_REG_X_BITS \ + MLX5_GET(flow_table_nic_cap, hcattr, \ + ft_header_modify_nic_receive.metadata_reg_c_x) +#define GET_TX_REG_X_BITS \ + MLX5_GET(flow_table_nic_cap, hcattr, \ + ft_header_modify_nic_transmit.metadata_reg_c_x) + + uint32_t tx_reg, rx_reg; + + tx_reg = GET_TX_REG_X_BITS; + rx_reg = GET_RX_REG_X_BITS; + attr->set_reg_c &= (rx_reg & tx_reg); + +#undef GET_RX_REG_X_BITS +#undef GET_TX_REG_X_BITS + } attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); attr->inner_ipv4_ihl = MLX5_GET (flow_table_nic_cap, hcattr, @@ -1163,6 +1181,18 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->esw_mgr_vport_id = MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); } + if (attr->eswitch_manager) { + uint32_t esw_reg; + + hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, + MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE | + MLX5_HCA_CAP_OPMOD_GET_CUR); + if (!hcattr) + return rc; + esw_reg = MLX5_GET(flow_table_esw_cap, hcattr, + ft_header_modify_esw_fdb.metadata_reg_c_x); + attr->set_reg_c &= esw_reg; + } return 0; error: rc = (rc > 0) ? -rc : rc; diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index cceaf3411d..a10aa3331b 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -263,6 +263,8 @@ struct mlx5_hca_attr { uint32_t crypto_wrapped_import_method:1; uint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */ uint16_t max_wqe_sz_sq; + uint32_t set_reg_c:8; + uint32_t nic_flow_table:1; uint32_t modify_outer_ip_ecn:1; }; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 9c1c93f916..ca4763f53d 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1295,6 +1295,7 @@ enum { MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1, MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1, MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, + MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE = 0x8 << 1, MLX5_SET_HCA_CAP_OP_MOD_ESW = 0x9 << 1, MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, MLX5_GET_HCA_CAP_OP_MOD_CRYPTO = 0x1A << 1, @@ -1892,6 +1893,7 @@ struct mlx5_ifc_roce_caps_bits { }; struct mlx5_ifc_ft_fields_support_bits { + /* set_action_field_support */ u8 outer_dmac[0x1]; u8 outer_smac[0x1]; u8 outer_ether_type[0x1]; @@ -1919,7 +1921,7 @@ struct mlx5_ifc_ft_fields_support_bits { u8 outer_gre_key[0x1]; u8 outer_vxlan_vni[0x1]; u8 reserved_at_1a[0x5]; - u8 source_eswitch_port[0x1]; + u8 source_eswitch_port[0x1]; /* end of DW0 */ u8 inner_dmac[0x1]; u8 inner_smac[0x1]; u8 inner_ether_type[0x1]; @@ -1943,8 +1945,33 @@ struct mlx5_ifc_ft_fields_support_bits { u8 inner_tcp_sport[0x1]; u8 inner_tcp_dport[0x1]; u8 inner_tcp_flags[0x1]; - u8 reserved_at_37[0x9]; - u8 reserved_at_40[0x40]; + u8 reserved_at_37[0x9]; /* end of DW1 */ + u8 reserved_at_40[0x20]; /* end of DW2 */ + u8 reserved_at_60[0x18]; + union { + struct { + u8 metadata_reg_c_7[0x1]; + u8 metadata_reg_c_6[0x1]; + u8 metadata_reg_c_5[0x1]; + u8 metadata_reg_c_4[0x1]; + u8 metadata_reg_c_3[0x1]; + u8 metadata_reg_c_2[0x1]; + u8 metadata_reg_c_1[0x1]; + u8 metadata_reg_c_0[0x1]; + }; + u8 metadata_reg_c_x[0x8]; + }; /* end of DW3 */ + /* set_action_field_support_2 */ + u8 reserved_at_80[0x80]; + /* add_action_field_support */ + u8 reserved_at_100[0x80]; + /* add_action_field_support_2 */ + u8 reserved_at_180[0x80]; + /* copy_action_field_support */ + u8 reserved_at_200[0x80]; + /* copy_action_field_support_2 */ + u8 reserved_at_280[0x80]; + u8 reserved_at_300[0x100]; }; /* @@ -1989,9 +2016,18 @@ struct mlx5_ifc_flow_table_nic_cap_bits { u8 reserved_at_e00[0x200]; struct mlx5_ifc_ft_fields_support_bits ft_header_modify_nic_receive; - u8 reserved_at_1080[0x380]; struct mlx5_ifc_ft_fields_support_2_bits ft_field_support_2_nic_receive; + u8 reserved_at_1480[0x780]; + struct mlx5_ifc_ft_fields_support_bits + ft_header_modify_nic_transmit; + u8 reserved_at_2000[0x6000]; +}; + +struct mlx5_ifc_flow_table_esw_cap_bits { + u8 reserved_at_0[0x800]; + struct mlx5_ifc_ft_fields_support_bits ft_header_modify_esw_fdb; + u8 reserved_at_C00[0x7400]; }; /* @@ -2046,6 +2082,7 @@ union mlx5_ifc_hca_cap_union_bits { struct mlx5_ifc_qos_cap_bits qos_cap; struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps; struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; + struct mlx5_ifc_flow_table_esw_cap_bits flow_table_esw_cap; struct mlx5_ifc_esw_cap_bits esw_cap; struct mlx5_ifc_roce_caps_bits roce_caps; u8 reserved_at_0[0x8000]; -- 2.18.1