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dkim=none (message not signed) header.d=none;dmarc=fail action=oreject header.from=nvidia.com; Received-SPF: None (protection.outlook.com: nvidia.com does not designate permitted sender hosts) Received: from mail.nvidia.com (216.228.117.161) by DM6NAM11FT032.mail.protection.outlook.com (10.13.173.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.16 via Frontend Transport; Thu, 20 Oct 2022 03:22:36 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Wed, 19 Oct 2022 20:22:27 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 19 Oct 2022 20:22:25 -0700 From: Suanming Mou To: Matan Azrad , Viacheslav Ovsiienko CC: , , Subject: [PATCH v5 01/18] net/mlx5: fix invalid flow attributes Date: Thu, 20 Oct 2022 06:21:53 +0300 Message-ID: <20221020032210.30250-2-suanmingm@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221020032210.30250-1-suanmingm@nvidia.com> References: <20220923144334.27736-1-suanmingm@nvidia.com> <20221020032210.30250-1-suanmingm@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT032:EE_|SA1PR12MB6821:EE_ X-MS-Office365-Filtering-Correlation-Id: 86199e91-28fb-470f-a739-08dab24a561a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Oct 2022 03:22:36.6539 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86199e91-28fb-470f-a739-08dab24a561a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6821 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In the function flow_get_drv_type(), attr will be read in non-HWS mode. In case user call the HWS API in SWS mode, attr should be placed in HWS functions, or it will cause crash. Fixes: c40c061a022e ("net/mlx5: add basic flow queue operation") Signed-off-by: Suanming Mou --- drivers/net/mlx5/mlx5_flow.c | 38 ++++++++++++++++++++++++------------ 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 2c6acd551c..f36e72fb89 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -3742,6 +3742,8 @@ flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr) */ if (priv->sh->config.dv_flow_en == 2) return MLX5_FLOW_TYPE_HW; + if (!attr) + return MLX5_FLOW_TYPE_MIN; /* If no OS specific type - continue with DV/VERBS selection */ if (attr->transfer && priv->sh->config.dv_esw_en) type = MLX5_FLOW_TYPE_DV; @@ -8254,8 +8256,9 @@ mlx5_flow_info_get(struct rte_eth_dev *dev, struct rte_flow_error *error) { const struct mlx5_flow_driver_ops *fops; + struct rte_flow_attr attr = {0}; - if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) + if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, @@ -8289,8 +8292,9 @@ mlx5_flow_port_configure(struct rte_eth_dev *dev, struct rte_flow_error *error) { const struct mlx5_flow_driver_ops *fops; + struct rte_flow_attr attr = {0}; - if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) + if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, @@ -8321,8 +8325,9 @@ mlx5_flow_pattern_template_create(struct rte_eth_dev *dev, struct rte_flow_error *error) { const struct mlx5_flow_driver_ops *fops; + struct rte_flow_attr fattr = {0}; - if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) { + if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, @@ -8352,8 +8357,9 @@ mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev, struct rte_flow_error *error) { const struct mlx5_flow_driver_ops *fops; + struct rte_flow_attr attr = {0}; - if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) + if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, @@ -8387,8 +8393,9 @@ mlx5_flow_actions_template_create(struct rte_eth_dev *dev, struct rte_flow_error *error) { const struct mlx5_flow_driver_ops *fops; + struct rte_flow_attr fattr = {0}; - if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) { + if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, @@ -8418,8 +8425,9 @@ mlx5_flow_actions_template_destroy(struct rte_eth_dev *dev, struct rte_flow_error *error) { const struct mlx5_flow_driver_ops *fops; + struct rte_flow_attr attr = {0}; - if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) + if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, @@ -8459,8 +8467,9 @@ mlx5_flow_table_create(struct rte_eth_dev *dev, struct rte_flow_error *error) { const struct mlx5_flow_driver_ops *fops; + struct rte_flow_attr fattr = {0}; - if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) { + if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, @@ -8496,8 +8505,9 @@ mlx5_flow_table_destroy(struct rte_eth_dev *dev, struct rte_flow_error *error) { const struct mlx5_flow_driver_ops *fops; + struct rte_flow_attr attr = {0}; - if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) + if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, @@ -8544,8 +8554,9 @@ mlx5_flow_async_flow_create(struct rte_eth_dev *dev, struct rte_flow_error *error) { const struct mlx5_flow_driver_ops *fops; + struct rte_flow_attr fattr = {0}; - if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) { + if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, @@ -8587,8 +8598,9 @@ mlx5_flow_async_flow_destroy(struct rte_eth_dev *dev, struct rte_flow_error *error) { const struct mlx5_flow_driver_ops *fops; + struct rte_flow_attr fattr = {0}; - if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) + if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, @@ -8623,8 +8635,9 @@ mlx5_flow_pull(struct rte_eth_dev *dev, struct rte_flow_error *error) { const struct mlx5_flow_driver_ops *fops; + struct rte_flow_attr attr = {0}; - if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) + if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, @@ -8652,8 +8665,9 @@ mlx5_flow_push(struct rte_eth_dev *dev, struct rte_flow_error *error) { const struct mlx5_flow_driver_ops *fops; + struct rte_flow_attr attr = {0}; - if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) + if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, -- 2.25.1