From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 09BF9A0553; Thu, 20 Oct 2022 17:59:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D2E5B4280E; Thu, 20 Oct 2022 17:59:09 +0200 (CEST) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2061.outbound.protection.outlook.com [40.107.244.61]) by mails.dpdk.org (Postfix) with ESMTP id 89B8441614 for ; Thu, 20 Oct 2022 17:59:08 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=SYuzAyWaqnVctnxB6LnWY0IZ8I+ZCsN8OGaovt6JcBOKSWso/7J+LGUT/WjW2buSfbAo878sKReyobkbKjAXAT5b4M50SvmAPTQ40KsVNDmuT6seJQ22GCkjQ0MhQZJtgSCvBZYu0B8dMHaK+odHvsjtIQ6XvhUv7sGSyBQj6SLNCG8oh1z7eO6+c78/aUGKJQ6MQ40jBBCb7VdEFgjt3pYVdRzkHcs4+2Y5/yUVv9ubMtuKurzRNnKqGjFnO9xgYsPKmCjzzzzxUyVWjfxPEkZI3ERD5VDvBFzF4tXpoUHMCNCKJwaKJSQ2HPUqQ2cxE1htYaFoHajpWnTMA/wwWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Dw3vZJpV15VCYI4asQ68u4xh1oEtxo19932fcBD5Ums=; b=eTmQclrdh2hrsdkWjneq1FH1t0ydv6d6SvMc1wSZ9kIoMYakpJu1HB1fdm5hNrFRMghT2tMji6oNW8ZEUjSGyLpf0k5yVsSRQ8+wmauYNwkf5UPI5rEtfhqY42W4ZMT/GjiFZQTIXSoRFs3qJ8BJ0CtLoOtuKymWYoRwyZAgCclVwXcdJbCXwDvIYfaMRsn/tRbsAKyFrLFZAjlxoalCfOb0h+K8OyFIty2OMapchi167yTHbz9dGW8rviym1sOpS2TOSTyiQZb5Eq5YyDqj0OUlFP5DI2DmGkhexlU3b6vjLCDm0eM1p2umQWOnJwkRsRzMFrQhsLKQHO9qy6RgeA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none (sender ip is 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=fail (p=reject sp=reject pct=100) action=oreject header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Dw3vZJpV15VCYI4asQ68u4xh1oEtxo19932fcBD5Ums=; b=snJbDmiY3UaTapXxAkWRT3Lvnit1a5WKnG7oCcKxO6a5sPI0MLTLjdThwomEk3rYM4Z1FPsgKSXmXqQUgQQSgxOiT396NXJ7+zoD7xi8bX41O8Bh49Kit9ESGymNL24nAXw8MzmFX0o+pv6hkygrsT2SA3QW9HW5+ykHGC+WwffG4axZtHa3BzON+N7levs94xBGODkChej6fRszK+sRx6m54n90Kn6msxBSdYwQfz3WiohuRGJViTekj7dAYrzL1JN0dHIqKXJlifU54LjJYGdYT8uK99ygzphXXjGL8Mlsnq3bRXydIjbBsp+6RZGH3eCUJtDjRroBbd/LaawGmg== Received: from DS7PR03CA0315.namprd03.prod.outlook.com (2603:10b6:8:2b::10) by PH7PR12MB7380.namprd12.prod.outlook.com (2603:10b6:510:20f::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.33; Thu, 20 Oct 2022 15:59:06 +0000 Received: from DM6NAM11FT097.eop-nam11.prod.protection.outlook.com (2603:10b6:8:2b:cafe::70) by DS7PR03CA0315.outlook.office365.com (2603:10b6:8:2b::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.34 via Frontend Transport; Thu, 20 Oct 2022 15:59:06 +0000 X-MS-Exchange-Authentication-Results: spf=none (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=fail action=oreject header.from=nvidia.com; Received-SPF: None (protection.outlook.com: nvidia.com does not designate permitted sender hosts) Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT097.mail.protection.outlook.com (10.13.172.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.16 via Frontend Transport; Thu, 20 Oct 2022 15:59:06 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 20 Oct 2022 08:58:55 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 20 Oct 2022 08:58:53 -0700 From: Alex Vesker To: , , , , Matan Azrad CC: , , Dariusz Sosnowski Subject: [v6 04/18] net/mlx5: add port to metadata conversion Date: Thu, 20 Oct 2022 18:57:34 +0300 Message-ID: <20221020155749.16643-5-valex@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221020155749.16643-1-valex@nvidia.com> References: <20220922190345.394-1-valex@nvidia.com> <20221020155749.16643-1-valex@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT097:EE_|PH7PR12MB7380:EE_ X-MS-Office365-Filtering-Correlation-Id: 6e5bebc8-392e-47c6-3739-08dab2b40461 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: M7KxjO6k3y3KCSiyBrFcWKy+gsccSOJsWPxeOeUY4/81jRbQMzwMoZiTYpCriZDw2/hbO3jgieIxVOiqXXsYRZ+aLB1yNERhVvwWgs5iElVTfkrlJLSVKLjhEFJJ58ozxgZZiaCMk4MYIYeckFPWtjN+crCRJnDBTamAzLgULF30QDpNLHnNUevtsMRX4+YhDAlCcGu2fU1u/8NKy5j3e7NJfosIShMPM4abNl2gl2tsQU853IWFyGx1wXP3cQJYXXxkZD1SZD7Q8Ricx5b9k5N9sdpHZxU6vGH9Oo9GZjBhrqCCjWGX2FBJz0JOOjupsyjd8oVt+t3fbnm1H7/V9v6PAPlBd+y63UgCX76v3hE5BHBKcuYjB1Gf6O8wNTTTMY3EGfb6wRS/cJDFeBspNb+3Ggu3/YJvoRq9Jed8rjBvu/9vuidPDKOjED++9E011Bno95xSdrCHH1OeVWbk+P5DNOGw0mPGqllb/VggXZOeAqjTPdD5NnELegPrbKUV93duILEyXfe5cTK4TM6LnglXhbH0mMz1rACVHu8K/Eqw3JVdfEDe8l+UY5kL4OA/zLi+oHOixi2zQACr1qzB5YMS/PFzLYDG7Kpk6aYUrfX3LBNY/edQItUyupdo7H1G7wnJnEBITNMGjBwmuBnr1UfVSRfVz323YiKRASyzXj5RtxGlsjUar/La0xsK01uf1Y1UY9Z0M87awKXKeZ2j3QHb5w4P5CLXAtd1U6qHGq3iCLscZ+VMfAi4HvIwaUrnQSh+tAKshHH07UxuVdiYWjcAQYmS+pwEAfD9sDmSf0JFXlZBHhLEqGBM/iXeSMQd X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(396003)(39860400002)(376002)(346002)(136003)(451199015)(46966006)(36840700001)(40470700004)(82310400005)(7636003)(36756003)(2616005)(478600001)(5660300002)(356005)(83380400001)(70206006)(6666004)(107886003)(47076005)(70586007)(4326008)(8676002)(55016003)(8936002)(41300700001)(7696005)(6286002)(86362001)(36860700001)(336012)(54906003)(6636002)(426003)(26005)(110136005)(16526019)(40460700003)(40480700001)(316002)(1076003)(186003)(2906002)(82740400003)(21314003)(309714004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Oct 2022 15:59:06.2277 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e5bebc8-392e-47c6-3739-08dab2b40461 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT097.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7380 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dariusz Sosnowski This patch initial version of functions used to: - convert between ethdev port_id and internal tag/mask value, - convert between IB context and internal tag/mask value. Signed-off-by: Dariusz Sosnowski --- drivers/net/mlx5/linux/mlx5_os.c | 10 +++++- drivers/net/mlx5/mlx5.c | 1 + drivers/net/mlx5/mlx5_flow.c | 6 ++++ drivers/net/mlx5/mlx5_flow.h | 52 ++++++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5_flow_hw.c | 29 ++++++++++++++++++ 5 files changed, 97 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 3e505d8f4c..d1e7bcce57 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1554,8 +1554,16 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, if (!priv->hrxqs) goto error; rte_rwlock_init(&priv->ind_tbls_lock); - if (priv->sh->config.dv_flow_en == 2) + if (priv->sh->config.dv_flow_en == 2) { +#ifdef HAVE_IBV_FLOW_DV_SUPPORT + if (priv->vport_meta_mask) + flow_hw_set_port_info(eth_dev); return eth_dev; +#else + DRV_LOG(ERR, "DV support is missing for HWS."); + goto error; +#endif + } /* Port representor shares the same max priority with pf port. */ if (!priv->sh->flow_priority_check_flag) { /* Supported Verbs flow priority number detection. */ diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 752b60d769..1d10932619 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1944,6 +1944,7 @@ mlx5_dev_close(struct rte_eth_dev *dev) mlx5_flex_item_port_cleanup(dev); #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) flow_hw_resource_release(dev); + flow_hw_clear_port_info(dev); #endif if (priv->rxq_privs != NULL) { /* XXX race condition if mlx5_rx_burst() is still running. */ diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 026d77b01f..72f4374c07 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -33,6 +33,12 @@ #include "mlx5_common_os.h" #include "rte_pmd_mlx5.h" +/* + * Shared array for quick translation between port_id and vport mask/values + * used for HWS rules. + */ +struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS]; + struct tunnel_default_miss_ctx { uint16_t *queue; __extension__ diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 3537eb3d66..c0c719dd8b 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1326,6 +1326,58 @@ struct mlx5_flow_split_info { uint64_t prefix_layers; /**< Prefix subflow layers. */ }; +struct flow_hw_port_info { + uint32_t regc_mask; + uint32_t regc_value; + uint32_t is_wire:1; +}; + +extern struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS]; + +/* + * Get metadata match tag and mask for given rte_eth_dev port. + * Used in HWS rule creation. + */ +static __rte_always_inline const struct flow_hw_port_info * +flow_hw_conv_port_id(const uint16_t port_id) +{ + struct flow_hw_port_info *port_info; + + if (port_id >= RTE_MAX_ETHPORTS) + return NULL; + port_info = &mlx5_flow_hw_port_infos[port_id]; + return !!port_info->regc_mask ? port_info : NULL; +} + +#ifdef HAVE_IBV_FLOW_DV_SUPPORT +/* + * Get metadata match tag and mask for the uplink port represented + * by given IB context. Used in HWS context creation. + */ +static __rte_always_inline const struct flow_hw_port_info * +flow_hw_get_wire_port(struct ibv_context *ibctx) +{ + struct ibv_device *ibdev = ibctx->device; + uint16_t port_id; + + MLX5_ETH_FOREACH_DEV(port_id, NULL) { + const struct mlx5_priv *priv = + rte_eth_devices[port_id].data->dev_private; + + if (priv && priv->master) { + struct ibv_context *port_ibctx = priv->sh->cdev->ctx; + + if (port_ibctx->device == ibdev) + return flow_hw_conv_port_id(port_id); + } + } + return NULL; +} +#endif + +void flow_hw_set_port_info(struct rte_eth_dev *dev); +void flow_hw_clear_port_info(struct rte_eth_dev *dev); + typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, const struct rte_flow_item items[], diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index b168ff9e7e..765e5164cb 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -2211,6 +2211,35 @@ flow_hw_resource_release(struct rte_eth_dev *dev) priv->nb_queue = 0; } +/* Sets vport tag and mask, for given port, used in HWS rules. */ +void +flow_hw_set_port_info(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + uint16_t port_id = dev->data->port_id; + struct flow_hw_port_info *info; + + MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS); + info = &mlx5_flow_hw_port_infos[port_id]; + info->regc_mask = priv->vport_meta_mask; + info->regc_value = priv->vport_meta_tag; + info->is_wire = priv->master; +} + +/* Clears vport tag and mask used for HWS rules. */ +void +flow_hw_clear_port_info(struct rte_eth_dev *dev) +{ + uint16_t port_id = dev->data->port_id; + struct flow_hw_port_info *info; + + MLX5_ASSERT(port_id < RTE_MAX_ETHPORTS); + info = &mlx5_flow_hw_port_infos[port_id]; + info->regc_mask = 0; + info->regc_value = 0; + info->is_wire = 0; +} + /** * Create shared action. * -- 2.18.1