From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7C538A0552; Thu, 20 Oct 2022 23:25:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F12D142BB7; Thu, 20 Oct 2022 23:24:45 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id B9B8E4281B; Thu, 20 Oct 2022 23:24:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301078; x=1697837078; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w4xotwoAj9Ovucgg2l9BF8Yq4JUc7WzCYcrVVZOz2SY=; b=MAuMoCsytyU4cxrROd3fIFeZ/2jxOFEtydG7QCspaHkZlKD6UjPAig6c pUB51sQPYD57zPYKMinVovPBD3xg1/16HNuimutezqX1o2VA5/Ivcomqn iQbvbfCNuahX8O2/kARGJm87R6X+RQASixBS5MNcvCSy/Si5anNifHAW5 DXADL+p5M7QACg5cEECjSEgmiIinc2kzfFtv3+018otGUHR6o4zi+vF3/ eoFwSk2LTg5uRsPpqmPiZ/f+jFA+1+1N9GUgwZym8KX5rgO4DSD3FRSAZ PGbRCIWcX9XWxB22RJUxNlqMaGdMHZ8a1zwBIV8qcQ1CZdYkuqYaCpJkE w==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887465" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887465" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396835" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396835" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:32 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v5 07/29] baseband/acc100: enforce additional check on FCW Date: Thu, 20 Oct 2022 22:20:40 -0700 Message-Id: <20221021052102.107141-8-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enforce additional check on Frame Control Word validity and add stronger alignment for decompression mode. Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas --- drivers/baseband/acc/acc100_pmd.h | 1 + drivers/baseband/acc/acc_common.h | 1 + drivers/baseband/acc/rte_acc100_pmd.c | 71 ++++++++++++++++++++++----- 3 files changed, 62 insertions(+), 11 deletions(-) diff --git a/drivers/baseband/acc/acc100_pmd.h b/drivers/baseband/acc/acc100_pmd.h index 9486e98521..eb6349c85a 100644 --- a/drivers/baseband/acc/acc100_pmd.h +++ b/drivers/baseband/acc/acc100_pmd.h @@ -87,6 +87,7 @@ #define ACC100_HARQ_DDR (512 * 1) #define ACC100_PRQ_DDR_VER 0x10092020 #define ACC100_DDR_TRAINING_MAX (5000) +#define ACC100_HARQ_ALIGN_COMP 256 struct acc100_registry_addr { unsigned int dma_ring_dl5g_hi; diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h index 6f141c95ce..97d10b8b40 100644 --- a/drivers/baseband/acc/acc_common.h +++ b/drivers/baseband/acc/acc_common.h @@ -120,6 +120,7 @@ #define ACC_ALGO_SPA 0 #define ACC_ALGO_MSA 1 +#define ACC_HARQ_ALIGN_64B 64 /* Helper macro for logging */ #define rte_acc_log(level, fmt, ...) \ diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index e8ec70d954..13a762cb80 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1040,6 +1040,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, uint16_t harq_index; uint32_t l; bool harq_prun = false; + uint32_t max_hc_in; fcw->qm = op->ldpc_dec.q_m; fcw->nfiller = op->ldpc_dec.n_filler; @@ -1089,13 +1090,22 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, harq_in_length = op->ldpc_dec.harq_combined_input.length; if (fcw->hcin_decomp_mode > 0) harq_in_length = harq_in_length * 8 / 6; - harq_in_length = RTE_ALIGN(harq_in_length, 64); - if ((harq_layout[harq_index].offset > 0) & harq_prun) { + + harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb + - op->ldpc_dec.n_filler); + + /* Alignment on next 64B - Already enforced from HC output */ + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC_HARQ_ALIGN_64B); + + /* Stronger alignment requirement when in decompression mode */ + if (fcw->hcin_decomp_mode > 0) + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC100_HARQ_ALIGN_COMP); + + if ((harq_layout[harq_index].offset > 0) && harq_prun) { rte_bbdev_log_debug("HARQ IN offset unexpected for now\n"); fcw->hcin_size0 = harq_layout[harq_index].size0; fcw->hcin_offset = harq_layout[harq_index].offset; - fcw->hcin_size1 = harq_in_length - - harq_layout[harq_index].offset; + fcw->hcin_size1 = harq_in_length - harq_layout[harq_index].offset; } else { fcw->hcin_size0 = harq_in_length; fcw->hcin_offset = 0; @@ -1107,6 +1117,21 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, fcw->hcin_size1 = 0; } + /* Enforce additional check on FCW validity */ + max_hc_in = RTE_ALIGN_CEIL(fcw->ncb - fcw->nfiller, ACC_HARQ_ALIGN_64B); + if ((fcw->hcin_size0 > max_hc_in) || + (fcw->hcin_size1 + fcw->hcin_offset > max_hc_in) || + ((fcw->hcin_size0 > fcw->hcin_offset) && + (fcw->hcin_size1 != 0))) { + rte_bbdev_log(ERR, " Invalid FCW : HCIn %d %d %d, Ncb %d F %d", + fcw->hcin_size0, fcw->hcin_size1, + fcw->hcin_offset, + fcw->ncb, fcw->nfiller); + /* Disable HARQ input in that case to carry forward */ + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; + fcw->hcin_en = 0; + } + fcw->itmax = op->ldpc_dec.iter_max; fcw->itstop = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE); @@ -1131,15 +1156,27 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, if (fcw->hcout_en > 0) { parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8) * op->ldpc_dec.z_c - op->ldpc_dec.n_filler; - k0_p = (fcw->k0 > parity_offset) ? - fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; + k0_p = (fcw->k0 > parity_offset) ? fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; ncb_p = fcw->ncb - op->ldpc_dec.n_filler; - l = k0_p + fcw->rm_e; + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX); harq_out_length = (uint16_t) fcw->hcin_size0; - harq_out_length = RTE_MIN(RTE_MAX(harq_out_length, l), ncb_p); - harq_out_length = (harq_out_length + 0x3F) & 0xFFC0; - if ((k0_p > fcw->hcin_size0 + ACC_HARQ_OFFSET_THRESHOLD) && - harq_prun) { + harq_out_length = RTE_MAX(harq_out_length, l); + + /* Stronger alignment when in compression mode */ + if (fcw->hcout_comp_mode > 0) + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, ACC100_HARQ_ALIGN_COMP); + + /* Cannot exceed the pruned Ncb circular buffer */ + harq_out_length = RTE_MIN(harq_out_length, ncb_p); + + /* Alignment on next 64B */ + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, ACC_HARQ_ALIGN_64B); + + /* Stronger alignment when in compression mode enforced again */ + if (fcw->hcout_comp_mode > 0) + harq_out_length = RTE_ALIGN_FLOOR(harq_out_length, ACC100_HARQ_ALIGN_COMP); + + if ((k0_p > fcw->hcin_size0 + ACC_HARQ_OFFSET_THRESHOLD) && harq_prun) { fcw->hcout_size0 = (uint16_t) fcw->hcin_size0; fcw->hcout_offset = k0_p & 0xFFC0; fcw->hcout_size1 = harq_out_length - fcw->hcout_offset; @@ -1148,6 +1185,14 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, fcw->hcout_size1 = 0; fcw->hcout_offset = 0; } + + if (fcw->hcout_size0 == 0) { + rte_bbdev_log(ERR, " Invalid FCW : HCout %d", + fcw->hcout_size0); + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE; + fcw->hcout_en = 0; + } + harq_layout[harq_index].offset = fcw->hcout_offset; harq_layout[harq_index].size0 = fcw->hcout_size0; } else { @@ -1188,6 +1233,10 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, /* Disable HARQ input in that case to carry forward */ op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; } + if (unlikely(fcw->rm_e == 0)) { + rte_bbdev_log(WARNING, "Null E input provided"); + fcw->rm_e = 2; + } fcw->hcin_en = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE); -- 2.37.1