From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AD955A054A; Tue, 25 Oct 2022 18:05:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A29C542C1F; Tue, 25 Oct 2022 18:05:46 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 8561942C1D; Tue, 25 Oct 2022 18:05:44 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29PFToC3006323; Tue, 25 Oct 2022 09:05:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=6v061wy9Qyt2OZCUcBHQ+goEFfkOKdOAMBFm7JzYvuM=; b=Hf4GTyvIPbKFoBHcjH6FQ5vEws9gLgFsEbjRkgfLjajn9VinCY+SXqlip78YuadeBcli WiSmZaYXoGa9PfpLYRYbkuKkDf731juypOk9jD/Y+J6R37PvGdN+be0dBTVb+7hrAXy7 fx2Xqnq36SNjjeBnTxcPKK+eV/nMRAiDrIyPu6kJoqhsS4p/lBvcHDKAyAzkIkPSRt02 5RmTtNGHFLeJAZCQq5RQv4LwfIfBMwy8MtG526xEUfPa+kdd3WpgbOkqfsOQAyl4DUA2 Sw6TwMnOgCUgt9wVadjtiBkylp/rObZtMhe6hVcZHhLjJVxPsHs66ZUKgZ7e+fNUYea2 KQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3kcg1muvsp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 25 Oct 2022 09:05:42 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 25 Oct 2022 09:05:40 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 25 Oct 2022 09:05:40 -0700 Received: from MININT-80QBFE8.corp.innovium.com (unknown [10.28.161.88]) by maili.marvell.com (Postfix) with ESMTP id BDF213F7087; Tue, 25 Oct 2022 09:05:37 -0700 (PDT) From: To: , , David Christensen CC: , Pavan Nikhilesh , , Shijith Thotton Subject: [PATCH v6 1/5] examples/l3fwd: fix port group mask generation Date: Tue, 25 Oct 2022 21:35:35 +0530 Message-ID: <20221025160539.14613-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011101207.4489-1-pbhagavatula@marvell.com> References: <20221011101207.4489-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: RRGbiEUyqSPYv8nSyw7kh75WolJ31cwi X-Proofpoint-GUID: RRGbiEUyqSPYv8nSyw7kh75WolJ31cwi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-25_09,2022-10-25_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Fix port group mask generation in altivec, vec_any_eq returns 0 or 1 while port_groupx4 expects comparison mask result. Fixes: 2193b7467f7a ("examples/l3fwd: optimize packet processing on powerpc") Cc: stable@dpdk.org Signed-off-by: Pavan Nikhilesh Acked-by: Shijith Thotton --- v6 Changes: - Minor optimiazation to process_dst_port NEON. v5 Changes: - Fix compilation errors. v4 Changes: - Fix missing `rte_free`. v3 Changes: - PPC optimize port mask generation. - Fix aarch32 compilation. v2 Changes: - Fix PPC, RISC-V, aarch32 compilation. examples/common/altivec/port_group.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/examples/common/altivec/port_group.h b/examples/common/altivec/port_group.h index 5e209b02fa..1c05bc025a 100644 --- a/examples/common/altivec/port_group.h +++ b/examples/common/altivec/port_group.h @@ -26,12 +26,17 @@ port_groupx4(uint16_t pn[FWDSTEP + 1], uint16_t *lp, uint16_t u16[FWDSTEP + 1]; uint64_t u64; } *pnum = (void *)pn; - + __vector unsigned long long result; + const __vector unsigned int perm_mask = {0x00204060, 0x80808080, + 0x80808080, 0x80808080}; int32_t v; - v = vec_any_eq(dp1, dp2); - + dp1 = (__vector unsigned short)vec_cmpeq(dp1, dp2); + dp1 = vec_mergeh(dp1, dp1); + result = (__vector unsigned long long)vec_vbpermq( + (__vector unsigned char)dp1, (__vector unsigned char)perm_mask); + v = result[1]; /* update last port counter. */ lp[0] += gptbl[v].lpv; -- 2.25.1