From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 08705A00C2; Wed, 2 Nov 2022 00:05:36 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 10518427EC; Wed, 2 Nov 2022 00:05:17 +0100 (CET) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 8132840E03 for ; Wed, 2 Nov 2022 00:05:11 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667343911; x=1698879911; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=0PgR81u8Ysp9pLrhQfr30kU+DcJ7ZjYsMy+8r7bK0C4=; b=GpiaWUEtPIe+Tfr41JNkDgNVwSOwuFYW7Rv778koMIknX5tMLLzfuek+ 0lAqX0XkF2W4Qt/z0aGws4zWRvjcRNdifR8j2d8QhrT11EjHWJJxwJ+62 TBvx4Fq2e1UZQqfUud1HXyTlJI5ApfofN2RGguZTiNWy1+6/l/iGa0Rpg aBtB9KF0J0LHpOsSSg1bA4fMMnXXpA4Xf+4DE2W0Ag4eQG0RpTOTqMpxy MRQVO9IF1MWg6htvZFD2dRTGkq0ewzINGJjg0CBD0T4Q5dVCDigR7ElSq RaDTH5nC/U7Xdon6jlUtQH6EVqQTeuFQmqafk7tbaxfcP8JZaxKH6OI3N g==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="373484040" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="373484040" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 16:05:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="585175104" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="585175104" Received: from unknown (HELO icx-npg-scs1-cp1.localdomain) ([10.233.180.245]) by orsmga003.jf.intel.com with ESMTP; 01 Nov 2022 16:05:10 -0700 From: Nicolas Chautru To: dev@dpdk.org, gakhil@marvell.com, maxime.coquelin@redhat.com, hernan.vargas@intel.com Subject: [PATCH v1 4/6] baseband/acc: fix PMON register values Date: Tue, 1 Nov 2022 16:04:57 -0700 Message-Id: <20221101230459.50891-5-nicolas.chautru@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221101230459.50891-1-nicolas.chautru@intel.com> References: <20221101230459.50891-1-nicolas.chautru@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Hernan Vargas Enable properly the PMon for ACC100. Previous commit was missing actual implementation and using incorrect register values. Fixes: b4bd57b74c8 ("baseband/acc100: configure PMON control registers") Signed-off-by: Hernan Vargas --- drivers/baseband/acc/acc100_pmd.h | 6 ++++-- drivers/baseband/acc/rte_acc100_pmd.c | 5 +++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/baseband/acc/acc100_pmd.h b/drivers/baseband/acc/acc100_pmd.h index 8c0aec5ed8..a48298650c 100644 --- a/drivers/baseband/acc/acc100_pmd.h +++ b/drivers/baseband/acc/acc100_pmd.h @@ -146,8 +146,8 @@ static const struct acc100_registry_addr pf_reg_addr = { .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf, .qman_group_func = HWPfQmgrGrpFunction0, .ddr_range = HWPfDmaVfDdrBaseRw, - .pmon_ctrl_a = HWVfPmACntrlRegVf, - .pmon_ctrl_b = HWVfPmBCntrlRegVf, + .pmon_ctrl_a = HWPfPermonACntrlRegVf, + .pmon_ctrl_b = HWPfPermonBCntrlRegVf, }; /* Structure holding registry addresses for VF */ @@ -177,6 +177,8 @@ static const struct acc100_registry_addr vf_reg_addr = { .depth_log1_offset = HWVfQmgrGrpDepthLog21Vf, .qman_group_func = HWVfQmgrGrpFunction0Vf, .ddr_range = HWVfDmaDdrBaseRangeRoVf, + .pmon_ctrl_a = HWVfPmACntrlRegVf, + .pmon_ctrl_b = HWVfPmBCntrlRegVf, }; #endif /* _RTE_ACC100_PMD_H_ */ diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index b6e500c6bc..2999a6a81a 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -479,6 +479,11 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) /* Read the populated cfg from ACC100 registers */ fetch_acc100_config(dev); + for (value = 0; value <= 2; value++) { + acc_reg_write(d, reg_addr->pmon_ctrl_a, value); + acc_reg_write(d, reg_addr->pmon_ctrl_b, value); + } + /* Release AXI from PF */ if (d->pf_device) acc_reg_write(d, HWPfDmaAxiControl, 1); -- 2.37.1