From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 579A0A00C2; Wed, 2 Nov 2022 04:51:42 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3C82640693; Wed, 2 Nov 2022 04:51:42 +0100 (CET) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 9719640223; Wed, 2 Nov 2022 04:51:39 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667361099; x=1698897099; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ayk1tVhEeXTIkqKvKoVdSJ7R8hzb+PLhSSAvGLGs0OM=; b=UDJ03bteqPRTS6C4Cuiyxe/py9sBBxfvITqwsr8X36V/F06HGfs6Tgxg t5OwEWw4bcWdt+NfslYiDW1q0MyYeH36HaqcP2q80l6xtH4U+x8xHxdWH NQj3FUfHVoSDLx/qRDEsGzXlvzKfjYY/ppqzIK2P/1oRI6X4Yk9FoC9Gh YO0Kr7b5CyXjFssrKUlh3MNNReRbrtEveFGlKFQSZ7olN11zkI0FGJwaJ wxkQWQb7ubhQ8NXu8MIygWxgwVyOFgF96jqdOrU+7e0MVA+XV54mM/07F GBtQ8A7YoBDoeLMomspn2YtMbJW2hjG2zy5ggG6D2GCluMc02WSFFjAUm w==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="310409869" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="310409869" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 20:51:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="776738328" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="776738328" Received: from unknown (HELO localhost.localdomain) ([10.190.193.12]) by fmsmga001.fm.intel.com with ESMTP; 01 Nov 2022 20:51:35 -0700 From: Abhishek Maheshwari To: maxime.coquelin@redhat.com, xiao.w.wang@intel.com Cc: dev@dpdk.org, stable@dpdk.org, chenbo.xia@intel.com, purna.chandra.mandal@intel.com, andy.pei@intel.com, Abhishek Maheshwari Subject: [PATCH v2] vdpa/ifc/base: wait for queue disable before saving q-state Date: Wed, 2 Nov 2022 08:52:15 +0530 Message-Id: <20221102032215.2108558-1-abhishek.maheshwari@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221025072302.1683505-1-abhishek.maheshwari@intel.com> References: <20221025072302.1683505-1-abhishek.maheshwari@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Some ifc hardware require synchronization between disabling a queue and saving queue-state from LM registers. When queue is disabled from vDPA driver, ifc device stops executing new virtio-cmds and then updates LM registers with used/avail index. Before saving the queue-state, vDPA driver should wait until the queue is disabled from backend. Fixes: 5d75517beffe ("vdpa/ifc/base: access block device registers") Cc: andy.pei@intel.com Cc: stable@dpdk.org Signed-off-by: Abhishek Maheshwari --- v2: * Fixing the styling issues * Addressing comment to avoid reading the register again after exhausting the tries --- drivers/vdpa/ifc/base/ifcvf.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/vdpa/ifc/base/ifcvf.c b/drivers/vdpa/ifc/base/ifcvf.c index f1e1474447..281366f2a0 100644 --- a/drivers/vdpa/ifc/base/ifcvf.c +++ b/drivers/vdpa/ifc/base/ifcvf.c @@ -257,6 +257,7 @@ ifcvf_hw_disable(struct ifcvf_hw *hw) u32 i; struct ifcvf_pci_common_cfg *cfg; u32 ring_state; + int q_disable_try; cfg = hw->common_cfg; if (!cfg) { @@ -275,6 +276,21 @@ ifcvf_hw_disable(struct ifcvf_hw *hw) continue; } + /* Some ifc hardware require synchronization between disabling a + * queue and saving queue-state from LM registers. When queue is + * disabled from vDPA driver, ifc device stops executing new + * virtio-cmds and then updates LM registers with used/avail + * index. Before saving the queue-state, vDPA driver waits until + * the queue is disabled from backend. + */ + q_disable_try = 10; + while (q_disable_try-- && IFCVF_READ_REG16(&cfg->queue_enable)) + msec_delay(10); + + if (q_disable_try > 0) + WARNINGOUT("Failed Q:%d disable, Saved state invalid\n", + i); + if (hw->device_type == IFCVF_BLK) ring_state = *(u32 *)(hw->lm_cfg + IFCVF_LM_RING_STATE_OFFSET + -- 2.31.1