From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7E6CFA00C2; Wed, 2 Nov 2022 14:45:22 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3408241145; Wed, 2 Nov 2022 14:45:22 +0100 (CET) Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2088.outbound.protection.outlook.com [40.107.100.88]) by mails.dpdk.org (Postfix) with ESMTP id C062940DF7; Wed, 2 Nov 2022 14:45:20 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nZ0DCBPfu/jFVOofzP+KTTjHOY9vs62SNnPQoeHFevusGP+bUJX553rdlLCEsAyF81Nzw4/Pk1WmSFt4clGFZaAzalgquAoG2yDaLnbHNMYI7QWeDAPym4Og5MUo3F0CfKb8E+F8r9TOpesIX0JPHYsrlTdnMo7vnzqAVE5tqrFIRPUt6vy2dzQxwH/rchpUqlWCFCvI88PMn6ZtmuzzCGBsakmr5szO3Lz3tQtlKyRF3vn+vltdYRn9tBUVG33YCW3PyWZRYWgK/8dhQhFwNhszHktgqIhNfomT20rJWikqkwD4pCTQU4ucqXrr8Au2t08lgLY3uAOJNlnKjzUQOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=gD60PZlC1+9sUfWey68JyDcsXYy6BQrguNhTFbx1ioc=; b=maGrq2aVGEZVZFSMInz3DH/SqAYt/dYfpMnLHMXnSvHz9uxKpxwwMH2TN0RfC5F8j8qQiFniTUfegIuLEcbPhr0Kt3CHdtDoizcVibwNhvJL/tsjIdm+uR0yLi8/nBzHg0TclT1cWlSc0hlukfwQ7EMMseijKZi1QsFmlOSfkzwF6YkHvIDUmDPUKfJGH0ZIX7kX72AE9l3yssDp7FVK/Pck8g6DRolOjWI5FD/44XrcWigyq1zmJxrzXOvteTikvQl5jF3XGj+/PkPluSA3EhtV3+CNJtaMAWTGNMUsGpuf6NsrnNQpZb158F0llyuUxZBnVhggvCTR+rowoKxgow== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gD60PZlC1+9sUfWey68JyDcsXYy6BQrguNhTFbx1ioc=; b=bAPfvBgePlxxErSL5vtAYI3x0KE1fQaaGkCdn9fhWNXt9rGFVLG7HgsombatJ1HLC2VCenwpHAUCjXTUf1UQjPDPR/9FpQuAhDiH/y3qdKSKh1/A34N1OKzkt8AVfeidiKBy1CoYL/vdQUhOwGnwN1ljnCImaEuhwYy+DZI4xnlPTtFwmLpsxDDk+INo1IgRmHYg9HBOeL3ISkALHNkzR/OxiT2TWPprVok5g34YhC4hnNLu+F1O+QvcWlIkOaSvCdOvBMY1zBlizCDVZSPVaLoXLFjGQYSgcM8KQh3CHZef+JZDKCCb1fCmoD4Ysj4P0rvn9gONlimbQqUJKvRRuw== Received: from BN9PR03CA0530.namprd03.prod.outlook.com (2603:10b6:408:131::25) by BY5PR12MB5509.namprd12.prod.outlook.com (2603:10b6:a03:1d7::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.21; Wed, 2 Nov 2022 13:45:18 +0000 Received: from BN8NAM11FT101.eop-nam11.prod.protection.outlook.com (2603:10b6:408:131:cafe::6d) by BN9PR03CA0530.outlook.office365.com (2603:10b6:408:131::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.21 via Frontend Transport; Wed, 2 Nov 2022 13:45:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT101.mail.protection.outlook.com (10.13.177.126) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.20 via Frontend Transport; Wed, 2 Nov 2022 13:45:18 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Wed, 2 Nov 2022 06:45:08 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 2 Nov 2022 06:45:06 -0700 From: Jiawei Wang To: , , Dekel Peled CC: , , Subject: [PATCH 2/2] net/mlx5: fix mirror flow validation with ASO action Date: Wed, 2 Nov 2022 15:44:14 +0200 Message-ID: <20221102134414.13573-3-jiaweiw@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221102134414.13573-1-jiaweiw@nvidia.com> References: <20221102134414.13573-1-jiaweiw@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT101:EE_|BY5PR12MB5509:EE_ X-MS-Office365-Filtering-Correlation-Id: 7fb08bfe-38e8-477f-3100-08dabcd87ac5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: D0zrwLAphw2nZ++HiuojpgT3+uvwTZs0k7egNQz39v11ONOhopTuXofcEbYNdN9u3zVYosPPz5Atv/rE71i/YvuN8Ww+kRxaM0EtoGQAcmD1rXByJiTtQbsGUb6OaD1djpD/l5HQQQQdKKRTRatWM6BY/ouUEv4wgfIse3Yb0JathzEsZItm+bnZ8Dsjm9/LkC8+D2g3IBWVb55AdNXgwW9xHd8Dy3mVtuTibc/nlzw80/4I4cXa6KqW+waWS/HMChVp4bMNVpHw/ORSNtXthMUJFIl8Z0YJw84Xe3EPIQI0xDbx32F328c8MBNijLFe6fxdDupUGunlqRhjK44Ig4SKU8jJZbOdtIRP2Fcwn8LEqMQqaglGNqPp5U27Z09IwBdgRqav/bJ9Mne2j3cSAJ3331rDoB+azRzbemySGzPYfPyqnuFc29OuVXp49cPKkFrfpTdKohD3wYxLlQeZAk0qcoPa2CCQby7Sc+mho28z2KGqjLz9Sknr7ZJETDavzldh1gHg4rpOEUxxIxoKmfkmk+KWapQFUUnF4Iz60heqsQB0fsC6lzDzEtPJ7nWgk1DGnYiq/T+7WuG9U67m3Q1ajRp/P6YVEXPSuvZoFoS7rLBwY8dWueF48X6IMA0bAUFmffKz/GDedFzgaKMd5vtpsyCVAjuEwSl2UlRu/qtzjoFZxy+m4eF9ImSa0lKlFj8El9ZLbJNGTjCKW/3j6vzVNiB2yjxk/NAY8oFYttE5RXlY5AkVgum+v74R+rEp1RL+re3YP+k/kiI9oJa5bA== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(396003)(39860400002)(136003)(346002)(376002)(451199015)(40470700004)(46966006)(36840700001)(47076005)(2906002)(83380400001)(426003)(86362001)(36860700001)(5660300002)(70586007)(82740400003)(356005)(7636003)(16526019)(70206006)(41300700001)(4326008)(336012)(8676002)(186003)(82310400005)(7696005)(110136005)(6666004)(26005)(40460700003)(6286002)(1076003)(2616005)(450100002)(316002)(6636002)(54906003)(8936002)(478600001)(40480700001)(36756003)(55016003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Nov 2022 13:45:18.3016 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7fb08bfe-38e8-477f-3100-08dabcd87ac5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT101.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB5509 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org While the ASO action(AGE, CT) with the sample action in the one E-switch mirror flow, due to hardware limitation, the ASO action after the sample action was not supported. This patch adds the checking for this validation and reject the flows with aso action after sample. Fixes: f935ed4b645a ("net/mlx5: support flow hit action for aging") Cc: stable@dpdk.org Signed-off-by: Jiawei Wang Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_dv.c | 53 ++++++++++++++++++++------------- 1 file changed, 32 insertions(+), 21 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index a2b85207b1..eabedfac17 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -5759,8 +5759,8 @@ flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry) * Pointer to the RSS action in sample action list. * @param[out] count * Pointer to the COUNT action in sample action list. - * @param[out] fdb_mirror_limit - * Pointer to the FDB mirror limitation flag. + * @param[out] fdb_mirror + * Pointer to the FDB mirror flag. * @param root * Whether action is on root table. * @param[out] error @@ -5778,9 +5778,8 @@ flow_dv_validate_action_sample(uint64_t *action_flags, const struct rte_flow_action_rss *rss, const struct rte_flow_action_rss **sample_rss, const struct rte_flow_action_count **count, - int *fdb_mirror_limit, + int *fdb_mirror, bool root, - struct mlx5_priv *act_priv, struct rte_flow_error *error) { struct mlx5_priv *priv = dev->data->dev_private; @@ -5968,9 +5967,7 @@ flow_dv_validate_action_sample(uint64_t *action_flags, NULL, "E-Switch must has a dest " "port for mirroring"); - if (!priv->sh->cdev->config.hca_attr.reg_c_preserve && - flow_source_vport_representor(priv, act_priv)) - *fdb_mirror_limit = 1; + *fdb_mirror = 1; } /* Continue validation for Xcap actions.*/ if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) && @@ -7056,7 +7053,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, uint16_t ether_type = 0; int actions_n = 0; uint8_t item_ipv6_proto = 0; - int fdb_mirror_limit = 0; + int fdb_mirror = 0; int modify_after_mirror = 0; const struct rte_flow_item *geneve_item = NULL; const struct rte_flow_item *gre_item = NULL; @@ -7122,6 +7119,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, const struct rte_flow_action_age *non_shared_age = NULL; const struct rte_flow_action_count *count = NULL; struct mlx5_priv *act_priv = NULL; + int aso_after_sample = 0; if (items == NULL) return -1; @@ -7902,12 +7900,6 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, error); if (ret) return ret; - if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && - fdb_mirror_limit) - return rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_ACTION, - NULL, - "sample and jump action combination is not supported"); ++actions_n; action_flags |= MLX5_FLOW_ACTION_JUMP; break; @@ -7987,6 +7979,8 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, RTE_FLOW_ERROR_TYPE_ACTION, NULL, "duplicate age actions set"); + if (action_flags & MLX5_FLOW_ACTION_SAMPLE) + aso_after_sample = 1; action_flags |= MLX5_FLOW_ACTION_AGE; ++actions_n; break; @@ -8014,6 +8008,9 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, RTE_FLOW_ERROR_TYPE_ACTION, NULL, "old age action and count must be in the same sub flow"); + } else { + if (action_flags & MLX5_FLOW_ACTION_SAMPLE) + aso_after_sample = 1; } action_flags |= MLX5_FLOW_ACTION_AGE; ++actions_n; @@ -8056,9 +8053,8 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, attr, item_flags, rss, &sample_rss, &sample_count, - &fdb_mirror_limit, + &fdb_mirror, is_root, - act_priv, error); if (ret < 0) return ret; @@ -8093,6 +8089,8 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, is_root, error); if (ret < 0) return ret; + if (action_flags & MLX5_FLOW_ACTION_SAMPLE) + aso_after_sample = 1; action_flags |= MLX5_FLOW_ACTION_CT; break; case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET: @@ -8350,11 +8348,24 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, NULL, "too many header modify" " actions to support"); } - /* Eswitch egress mirror and modify flow has limitation on CX5 */ - if (fdb_mirror_limit && modify_after_mirror) - return rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_ACTION, NULL, - "sample before modify action is not supported"); + if (fdb_mirror) { + if (!priv->sh->cdev->config.hca_attr.reg_c_preserve && + flow_source_vport_representor(priv, act_priv)) { + /* Eswitch egress mirror and modify flow has limitation on CX5 */ + if (modify_after_mirror) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "sample before modify action is not supported"); + if (action_flags & MLX5_FLOW_ACTION_JUMP) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "sample and jump action combination is not supported"); + } + if (aso_mask > 0 && aso_after_sample && fdb_mirror) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "sample before ASO action is not supported"); + } /* * Validation the NIC Egress flow on representor, except implicit * hairpin default egress flow with TX_QUEUE item, other flows not -- 2.18.1