From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1FA35A0093; Mon, 7 Nov 2022 08:05:05 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DAD2742D1D; Mon, 7 Nov 2022 08:05:03 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 25F6642D1D for ; Mon, 7 Nov 2022 08:05:02 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C5E0A23A; Sun, 6 Nov 2022 23:05:07 -0800 (PST) Received: from net-x86-dell-8268.shanghai.arm.com (net-x86-dell-8268.shanghai.arm.com [10.169.210.116]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 170393F534; Sun, 6 Nov 2022 23:04:58 -0800 (PST) From: Feifei Wang To: Ruifeng Wang Cc: dev@dpdk.org, david.hunt@intel.com, david.marchand@redhat.com, thomas@monjalon.net, stephen@networkplumber.org, nd@arm.com, Feifei Wang Subject: [PATCH v2 1/3] eal: add 8 bits case for wait scheme Date: Mon, 7 Nov 2022 15:04:47 +0800 Message-Id: <20221107070449.3319078-2-feifei.wang2@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221107070449.3319078-1-feifei.wang2@arm.com> References: <20220825064251.2637274-1-feifei.wang2@arm.com> <20221107070449.3319078-1-feifei.wang2@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For wait scheme generic helper, add 8 bits case. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang --- lib/eal/arm/include/rte_pause_64.h | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/lib/eal/arm/include/rte_pause_64.h b/lib/eal/arm/include/rte_pause_64.h index fe4d42b1ea..c21600ca96 100644 --- a/lib/eal/arm/include/rte_pause_64.h +++ b/lib/eal/arm/include/rte_pause_64.h @@ -31,6 +31,25 @@ static inline void rte_pause(void) /* Put processor into low power WFE(Wait For Event) state. */ #define __RTE_ARM_WFE() { asm volatile("wfe" : : : "memory"); } +/* + * Atomic exclusive load from addr, it returns the 8-bit content of + * *addr while making it 'monitored', when it is written by someone + * else, the 'monitored' state is cleared and an event is generated + * implicitly to exit WFE. + */ +#define __RTE_ARM_LOAD_EXC_8(src, dst, memorder) { \ + if (memorder == __ATOMIC_RELAXED) { \ + asm volatile("ldxrb %w[tmp], [%x[addr]]" \ + : [tmp] "=&r" (dst) \ + : [addr] "r" (src) \ + : "memory"); \ + } else { \ + asm volatile("ldaxrb %w[tmp], [%x[addr]]" \ + : [tmp] "=&r" (dst) \ + : [addr] "r" (src) \ + : "memory"); \ + } } + /* * Atomic exclusive load from addr, it returns the 16-bit content of * *addr while making it 'monitored', when it is written by someone @@ -111,9 +130,11 @@ static inline void rte_pause(void) } } \ #define __RTE_ARM_LOAD_EXC(src, dst, memorder, size) { \ - RTE_BUILD_BUG_ON(size != 16 && size != 32 && \ - size != 64 && size != 128); \ - if (size == 16) \ + RTE_BUILD_BUG_ON(size != 8 && size != 16 && \ + size != 32 && size != 64 && size != 128); \ + if (size == 8) \ + __RTE_ARM_LOAD_EXC_8(src, dst, memorder) \ + else if (size == 16) \ __RTE_ARM_LOAD_EXC_16(src, dst, memorder) \ else if (size == 32) \ __RTE_ARM_LOAD_EXC_32(src, dst, memorder) \ -- 2.25.1