From: Gregory Etelson <getelson@nvidia.com>
To: <dev@dpdk.org>
Cc: <getelson@nvidia.com>, <matan@nvidia.com>, <rasland@nvidia.com>,
<stable@dpdk.org>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Subject: [PATCH] common/mlx5: fix DevX register read error severity
Date: Thu, 10 Nov 2022 15:05:20 +0200 [thread overview]
Message-ID: <20221110130520.15275-1-getelson@nvidia.com> (raw)
PMD attempt to read HW UTC counter properties can fail because the feature
has no support in port FW or mlx5 kernel module.
In that case PMD still can produce correct time-stamps if it runs on core with
nanosecond time resolution.
Fixes: b0067860959d ("common/mlx5: update log for DevX general command failure")
Cc: stable@dpdk.org
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 05b9429c7f..59cebb530f 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -111,7 +111,7 @@ mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
MLX5_ST_SZ_BYTES(access_register_out) +
sizeof(uint32_t) * dw_cnt);
if (rc || MLX5_FW_STATUS(out)) {
- DEVX_DRV_LOG(ERR, out, "read access", "NIC register", reg_id);
+ DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id);
return MLX5_DEVX_ERR_RC(rc);
}
memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
--
2.34.1
next reply other threads:[~2022-11-10 13:05 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-10 13:05 Gregory Etelson [this message]
2022-11-10 16:18 ` David Marchand
2022-11-10 17:17 ` Raslan Darawsheh
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