From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D634AA0093; Thu, 8 Dec 2022 21:20:50 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 644C242D85; Thu, 8 Dec 2022 21:19:27 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 9F0C142D30 for ; Thu, 8 Dec 2022 21:19:14 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2B8JjZgh001924 for ; Thu, 8 Dec 2022 12:19:13 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=jwvsW1/kN9Xyrk3uBY6gtNNzZQhKaHyM7J+AFB2lHLo=; b=P1pNCBltJ9rpRslA2iVZ0h5RCR5n466sEZI7Bf5IXgGxXk5jWvXy5YLg6N+gkd9TZYrP rgtohMVOg4gVSgyUDR0A7b8OzFp0T4I6ipdpVwfI4gSi34WW3BCeOBiTClu+ZYmcEVA/ 0mZRNzzN0McpORI31uHK09cBhw8qWJ08r0jBEZRwxCAAGuMlafvJXyHz+rLCR/nys9/r jleSX1Yd7vvc6zAe3gIe/Kzt9UV5zZu9cdvvPKiHM7z3tdwn7PeGk4wNJWfQOZIRxh3L nZ+H4QpAe4nWcIQhAWrWRLKeulek9ndMlzdI+KVlstaW81E/slC/XntInXzgy9PVpn0R QQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3mb22svrmu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 08 Dec 2022 12:19:12 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 8 Dec 2022 12:19:11 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 8 Dec 2022 12:19:11 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id 3D34A3F70BE; Thu, 8 Dec 2022 12:18:16 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , Subject: [PATCH v2 16/37] ml/cnxk: add support to reserve and free OCM pages Date: Thu, 8 Dec 2022 12:17:44 -0800 Message-ID: <20221208201806.21893-17-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221208201806.21893-1-syalavarthi@marvell.com> References: <20221208200220.20267-1-syalavarthi@marvell.com> <20221208201806.21893-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: 3chYwmarooUaeY26-x-qVys0iQPMlJ1X X-Proofpoint-GUID: 3chYwmarooUaeY26-x-qVys0iQPMlJ1X X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-08_11,2022-12-08_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added support to reserve and free OCM pages for a model. OCM pages are reserved upon completion of model start and are released after model stop. Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_ocm.c | 131 ++++++++++++++++++++++++++++++++- drivers/ml/cnxk/cn10k_ml_ocm.h | 3 + 2 files changed, 131 insertions(+), 3 deletions(-) diff --git a/drivers/ml/cnxk/cn10k_ml_ocm.c b/drivers/ml/cnxk/cn10k_ml_ocm.c index a465848558..ddc0936cec 100644 --- a/drivers/ml/cnxk/cn10k_ml_ocm.c +++ b/drivers/ml/cnxk/cn10k_ml_ocm.c @@ -5,14 +5,17 @@ #include #include "cn10k_ml_dev.h" +#include "cn10k_ml_model.h" #include "cn10k_ml_ocm.h" #include "roc_api.h" /* OCM macros */ -#define BYTE_LEN 8 -#define OCM_MAP_WORD_SIZE (sizeof(uint8_t) * BYTE_LEN) -#define SET_BIT(num, n) ((num) | (1 << (n))) +#define BYTE_LEN 8 +#define OCM_MAP_WORD_SIZE (sizeof(uint8_t) * BYTE_LEN) +#define IS_BIT_SET(num, n) ((num) & (1 << (n))) +#define SET_BIT(num, n) ((num) | (1 << (n))) +#define CLEAR_BIT(num, n) ((num) &= ~((1) << (n))) /* Left shift multi-word mask by 1 bit. * @@ -333,3 +336,125 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w return wb_page_start; } + +void +cn10k_ml_ocm_reserve_pages(struct rte_ml_dev *dev, int16_t model_id, uint64_t tilemask, + int wb_page_start, uint16_t wb_pages, uint16_t scratch_pages) +{ + struct cn10k_ml_model *model; + struct cn10k_ml_dev *mldev; + struct cn10k_ml_ocm *ocm; + + int scratch_page_start; + int scratch_page_end; + int wb_page_end; + int tile_start; + int tile_end; + int tile_id; + int page_id; + + mldev = dev->data->dev_private; + ocm = &mldev->ocm; + model = dev->data->models[model_id]; + + /* Get first set bit, tile_start */ + tile_start = 0; + tile_end = 0; + cn10k_ml_ocm_tilecount(tilemask, &tile_start, &tile_end); + wb_page_end = wb_page_start + wb_pages - 1; + scratch_page_start = ocm->num_pages - scratch_pages; + scratch_page_end = ocm->num_pages - 1; + + /* Update tile_ocm_info */ + for (tile_id = tile_start; tile_id <= tile_end; tile_id++) { + /* Scratch pages */ + for (page_id = scratch_page_start; page_id <= scratch_page_end; page_id++) + ocm->tile_ocm_info[tile_id].ocm_mask[page_id / OCM_MAP_WORD_SIZE] = SET_BIT( + ocm->tile_ocm_info[tile_id].ocm_mask[page_id / OCM_MAP_WORD_SIZE], + page_id % OCM_MAP_WORD_SIZE); + ocm->tile_ocm_info[tile_id].scratch_pages = + PLT_MAX(ocm->tile_ocm_info[tile_id].scratch_pages, scratch_pages); + + /* WB pages */ + for (page_id = wb_page_start; page_id <= wb_page_end; page_id++) + ocm->tile_ocm_info[tile_id].ocm_mask[page_id / OCM_MAP_WORD_SIZE] = SET_BIT( + ocm->tile_ocm_info[tile_id].ocm_mask[page_id / OCM_MAP_WORD_SIZE], + page_id % OCM_MAP_WORD_SIZE); + if (wb_pages != 0) + ocm->tile_ocm_info[tile_id].last_wb_page = + PLT_MAX(ocm->tile_ocm_info[tile_id].last_wb_page, wb_page_end); + } + + model->addr.tile_start = tile_start; + model->addr.tile_end = tile_end; + + plt_ml_dbg("model_id = %d, tilemask = 0x%016lx", model_id, tilemask); + plt_ml_dbg("model_id = %d, wb_page_start = %d, wb_page_end = %d", model_id, wb_page_start, + wb_page_end); + plt_ml_dbg("model_id = %d, scratch_page_start = %d, scratch_page_end = %d", model_id, + scratch_page_start, scratch_page_end); +} + +void +cn10k_ml_ocm_free_pages(struct rte_ml_dev *dev, int16_t model_id) +{ + struct cn10k_ml_model *model; + struct cn10k_ml_dev *mldev; + struct cn10k_ml_ocm *ocm; + + int scratch_resize_pages; + int wb_page_start; + int wb_page_end; + int prev_start; + int curr_start; + int tile_id; + int page_id; + int16_t i; + + mldev = dev->data->dev_private; + ocm = &mldev->ocm; + model = dev->data->models[model_id]; + + /* Update OCM info for WB memory */ + wb_page_start = model->model_mem_map.wb_page_start; + wb_page_end = wb_page_start + model->model_mem_map.wb_pages - 1; + for (tile_id = model->addr.tile_start; tile_id <= model->addr.tile_end; tile_id++) { + for (page_id = wb_page_start; page_id <= wb_page_end; page_id++) { + ocm->tile_ocm_info[tile_id].ocm_mask[page_id / OCM_MAP_WORD_SIZE] = + CLEAR_BIT(ocm->tile_ocm_info[tile_id] + .ocm_mask[page_id / OCM_MAP_WORD_SIZE], + page_id % OCM_MAP_WORD_SIZE); + } + + /* Update last_wb_page size */ + if (wb_page_end == ocm->tile_ocm_info[tile_id].last_wb_page) + ocm->tile_ocm_info[tile_id].last_wb_page = wb_page_start - 1; + + /* Update scratch page size and clear extra bits */ + scratch_resize_pages = 0; + /* Get max scratch pages required, excluding the current model */ + for (i = 0; i < dev->data->nb_models; i++) { + struct cn10k_ml_model *model = dev->data->models[i]; + + if ((i != model_id) && (model != NULL)) { + if (IS_BIT_SET(model->model_mem_map.tilemask, tile_id)) + scratch_resize_pages = + PLT_MAX((int)model->model_mem_map.scratch_pages, + scratch_resize_pages); + } + } + + /* Clear extra scratch pages */ + if (scratch_resize_pages < ocm->tile_ocm_info[tile_id].scratch_pages) { + prev_start = ocm->num_pages - ocm->tile_ocm_info[tile_id].scratch_pages; + curr_start = ocm->num_pages - scratch_resize_pages; + for (page_id = prev_start; page_id < curr_start; page_id++) { + ocm->tile_ocm_info[tile_id].ocm_mask[page_id / OCM_MAP_WORD_SIZE] = + CLEAR_BIT(ocm->tile_ocm_info[tile_id] + .ocm_mask[page_id / OCM_MAP_WORD_SIZE], + page_id % OCM_MAP_WORD_SIZE); + } + ocm->tile_ocm_info[tile_id].scratch_pages = scratch_resize_pages; + } + } +} diff --git a/drivers/ml/cnxk/cn10k_ml_ocm.h b/drivers/ml/cnxk/cn10k_ml_ocm.h index 2b7166bbca..7c6b1432c5 100644 --- a/drivers/ml/cnxk/cn10k_ml_ocm.h +++ b/drivers/ml/cnxk/cn10k_ml_ocm.h @@ -80,5 +80,8 @@ struct cn10k_ml_ocm { int cn10k_ml_ocm_tilecount(uint64_t tilemask, int *start, int *end); int cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t wb_pages, uint16_t scratch_pages, uint64_t *tilemask); +void cn10k_ml_ocm_reserve_pages(struct rte_ml_dev *dev, int16_t model_id, uint64_t tilemask, + int wb_page_start, uint16_t wb_pages, uint16_t scratch_pages); +void cn10k_ml_ocm_free_pages(struct rte_ml_dev *dev, int16_t model_id); #endif /* _CN10K_ML_OCM_H_ */ -- 2.17.1