From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <dev-bounces@dpdk.org> Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3CA4EA00C5; Tue, 20 Dec 2022 04:48:03 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8B4E542D0D; Tue, 20 Dec 2022 04:48:00 +0100 (CET) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id 2F84940685 for <dev@dpdk.org>; Tue, 20 Dec 2022 04:47:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671508078; x=1703044078; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=WDcB+w/tNgMS9GSxSTYToRreESFFhiAUC3HgbnMUd8w=; b=es+22+nMU5cUHjWHcZ/qGp81qFv1z+R1s3tNhzCdiWq6lhtf/PQE6VVe 15hqtPZbnGOkv3p2YhcQzxAf2u5SGZ9tQiRj+R7kp7KiLMU0Y8oAP0Loi XttoIkWMoOKS+azmB/4XXajSqzrSyls4BeHg7Mhbwud+90/mlGMS4ABUi J/pJGC1HiUuHAn7prITvNnU/fCV/8bri+QtXr/sUKx3S/x1MGnWwz4bzl M5VaCKosJxsvvF1gQJzUoXiJbRG41PbFPNA1h84MxEylR0M9LeLZejm5M yq5LCP/t3JFhqYTKF2WuOistnuknTu0VXoGux20sWB5Z7bVgek/Aa3qcH Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="299198842" X-IronPort-AV: E=Sophos;i="5.96,258,1665471600"; d="scan'208";a="299198842" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2022 19:47:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="719378284" X-IronPort-AV: E=Sophos;i="5.96,258,1665471600"; d="scan'208";a="719378284" Received: from unknown (HELO npg-dpdk-simeisu-cvl-119d218.sh.intel.com) ([10.67.119.208]) by fmsmga004.fm.intel.com with ESMTP; 19 Dec 2022 19:47:56 -0800 From: Simei Su <simei.su@intel.com> To: qi.z.zhang@intel.com, junfeng.guo@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, Simei Su <simei.su@intel.com> Subject: [PATCH 1/2] net/igc/base: support Tx timestamp offload Date: Tue, 20 Dec 2022 11:47:40 +0800 Message-Id: <20221220034741.447037-2-simei.su@intel.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20221220034741.447037-1-simei.su@intel.com> References: <20221220034741.447037-1-simei.su@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Add definitions for Tx timestamp offload "RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP". Signed-off-by: Simei Su <simei.su@intel.com> --- drivers/net/igc/base/igc_defines.h | 9 +++++++++ drivers/net/igc/base/igc_regs.h | 8 ++++++++ 2 files changed, 17 insertions(+) diff --git a/drivers/net/igc/base/igc_defines.h b/drivers/net/igc/base/igc_defines.h index dd7330a..280570b 100644 --- a/drivers/net/igc/base/igc_defines.h +++ b/drivers/net/igc/base/igc_defines.h @@ -188,6 +188,15 @@ #define IGC_RCTL_BSEX 0x02000000 /* Buffer size extension */ #define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ +#define IGC_DTXMXPKTSZ_TSN 0x19 /* 1600 bytes of max TX DMA packet size */ +#define IGC_TXPBSIZE_TSN 0x04145145 /* 5k bytes buffer for each queue */ + +/* Transmit Scheduling */ +#define IGC_TQAVCTRL_TRANSMIT_MODE_TSN 0x00000001 +#define IGC_TQAVCTRL_ENHANCED_QAV 0x00000008 + +#define IGC_TXQCTL_QUEUE_MODE_LAUNCHT 0x00000001 + /* Use byte values for the following shift parameters * Usage: * psrctl |= (((ROUNDUP(value0, 128) >> IGC_PSRCTL_BSIZE0_SHIFT) & diff --git a/drivers/net/igc/base/igc_regs.h b/drivers/net/igc/base/igc_regs.h index d424387..e423814 100644 --- a/drivers/net/igc/base/igc_regs.h +++ b/drivers/net/igc/base/igc_regs.h @@ -602,6 +602,14 @@ #define IGC_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ #define IGC_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ +#define IGC_QBVCYCLET 0x331C +#define IGC_QBVCYCLET_S 0x3320 +#define IGC_STQT(_n) (0x3324 + 0x4 * (_n)) +#define IGC_ENDQT(_n) (0x3334 + 0x4 * (_n)) +#define IGC_TXQCTL(_n) (0x3344 + 0x4 * (_n)) +#define IGC_BASET_L 0x3314 +#define IGC_BASET_H 0x3318 + /* Filtering Registers */ #define IGC_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */ #define IGC_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */ -- 2.9.5