From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3A7EDA0545; Tue, 20 Dec 2022 20:27:12 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 40C1C42D1A; Tue, 20 Dec 2022 20:26:58 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3121B40A7A for ; Tue, 20 Dec 2022 20:26:54 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BKHPQ0p015491; Tue, 20 Dec 2022 11:26:53 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=byW8TMHKW3ZjWLwgqz+Rv+VJBD2Wr3QFCRm+2wRnu9g=; b=ePRblIFycEe82BUW2OfhWXhuQG6NI1HI0e0u8De0OIvmDDZcGd05LC9zD60nqXZSEQBI Tv4RcuaAJ8ikrAiAG1ycEPPwZptj5h5lCvJNG9dO/FvGMZPgQOfDnp03EALU5sPjrEZI GHx+v7mlOky/gxq1lUpWEySJny526zQyCSwKwANmeTPSlNvi0IOGWCkuGuidbkCnP7yc 6HDPHIpLDhJ9ThJhgsbDSR+d52yfh9Fk+a3HgxoeyfKFqxRmS2jfWvVaB8w06a/DvEIp sVc/0zFD93PSqjg1oAREoi1BNjJbGpjo0hr6S12DDCw2B/Op+4Mn09YEQu2EgktIt+ST 5w== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3mkapj2tpd-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 20 Dec 2022 11:26:53 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 20 Dec 2022 11:26:51 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Tue, 20 Dec 2022 11:26:51 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id 759583F7075; Tue, 20 Dec 2022 11:26:51 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi , Anatoly Burakov CC: , , , Subject: [PATCH v3 03/38] ml/cnxk: enable probe and remove of ML device Date: Tue, 20 Dec 2022 11:26:10 -0800 Message-ID: <20221220192645.14042-4-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221220192645.14042-1-syalavarthi@marvell.com> References: <20221208201806.21893-1-syalavarthi@marvell.com> <20221220192645.14042-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: WiWgFOSpNqxPeBXTFzrTsOXB7joJyKWl X-Proofpoint-GUID: WiWgFOSpNqxPeBXTFzrTsOXB7joJyKWl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-20_06,2022-12-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org ML inference engine on cn10k platform is a PCI based device. Added driver support to probe and remove the device for cn10k poll mode driver. The device is named by the PMD as "ml_cn10k". Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_dev.c | 114 +++++++++++++++++++++++++++++++++ drivers/ml/cnxk/cn10k_ml_dev.h | 11 ++++ drivers/ml/cnxk/cn10k_ml_ops.c | 10 +++ drivers/ml/cnxk/cn10k_ml_ops.h | 11 ++++ drivers/ml/cnxk/meson.build | 2 + 5 files changed, 148 insertions(+) create mode 100644 drivers/ml/cnxk/cn10k_ml_ops.c create mode 100644 drivers/ml/cnxk/cn10k_ml_ops.h diff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c index cc96a7bdb3..c2e93c9a1a 100644 --- a/drivers/ml/cnxk/cn10k_ml_dev.c +++ b/drivers/ml/cnxk/cn10k_ml_dev.c @@ -2,7 +2,121 @@ * Copyright (c) 2022 Marvell. */ +#include +#include #include #include +#include + +#include #include "cn10k_ml_dev.h" +#include "cn10k_ml_ops.h" + +/* Dummy operations for ML device */ +struct rte_ml_dev_ops ml_dev_dummy_ops = {0}; + +static int +cn10k_ml_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) +{ + struct rte_ml_dev_pmd_init_params init_params; + struct cn10k_ml_dev *mldev; + char name[RTE_ML_STR_MAX]; + struct rte_ml_dev *dev; + int ret; + + PLT_SET_USED(pci_drv); + + init_params = (struct rte_ml_dev_pmd_init_params){ + .socket_id = rte_socket_id(), .private_data_size = sizeof(struct cn10k_ml_dev)}; + + ret = roc_plt_init(); + if (ret < 0) { + plt_err("Failed to initialize platform model"); + return ret; + } + + rte_pci_device_name(&pci_dev->addr, name, sizeof(name)); + dev = rte_ml_dev_pmd_create(name, &pci_dev->device, &init_params); + if (dev == NULL) { + ret = -ENODEV; + goto error_exit; + } + + /* Get private data space allocated */ + mldev = dev->data->dev_private; + + if (rte_eal_process_type() == RTE_PROC_PRIMARY) { + mldev->roc.pci_dev = pci_dev; + + ret = roc_ml_dev_init(&mldev->roc); + if (ret) { + plt_err("Failed to initialize ML ROC, ret = %d", ret); + goto pmd_destroy; + } + + dev->dev_ops = &cn10k_ml_ops; + } else { + plt_err("CN10K ML Ops are not supported on secondary process"); + dev->dev_ops = &ml_dev_dummy_ops; + } + + dev->enqueue_burst = NULL; + dev->dequeue_burst = NULL; + dev->op_error_get = NULL; + + return 0; + +pmd_destroy: + rte_ml_dev_pmd_destroy(dev); + +error_exit: + plt_err("Could not create device (vendor_id: 0x%x device_id: 0x%x)", pci_dev->id.vendor_id, + pci_dev->id.device_id); + + return ret; +} + +static int +cn10k_ml_pci_remove(struct rte_pci_device *pci_dev) +{ + struct cn10k_ml_dev *mldev; + char name[RTE_ML_STR_MAX]; + struct rte_ml_dev *dev; + int ret; + + if (pci_dev == NULL) + return -EINVAL; + + rte_pci_device_name(&pci_dev->addr, name, sizeof(name)); + + dev = rte_ml_dev_pmd_get_named_dev(name); + if (dev == NULL) + return -ENODEV; + + if (rte_eal_process_type() == RTE_PROC_PRIMARY) { + mldev = dev->data->dev_private; + ret = roc_ml_dev_fini(&mldev->roc); + if (ret) + return ret; + } + + return rte_ml_dev_pmd_destroy(dev); +} + +static struct rte_pci_id pci_id_ml_table[] = { + {RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_ML_PF)}, + /* sentinel */ + {}, +}; + +static struct rte_pci_driver cn10k_mldev_pmd = { + .id_table = pci_id_ml_table, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA, + .probe = cn10k_ml_pci_probe, + .remove = cn10k_ml_pci_remove, +}; + +RTE_PMD_REGISTER_PCI(MLDEV_NAME_CN10K_PMD, cn10k_mldev_pmd); +RTE_PMD_REGISTER_PCI_TABLE(MLDEV_NAME_CN10K_PMD, pci_id_ml_table); +RTE_PMD_REGISTER_KMOD_DEP(MLDEV_NAME_CN10K_PMD, "vfio-pci"); diff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h index 049ac13fcd..833a09791a 100644 --- a/drivers/ml/cnxk/cn10k_ml_dev.h +++ b/drivers/ml/cnxk/cn10k_ml_dev.h @@ -5,4 +5,15 @@ #ifndef _CN10K_ML_DEV_H_ #define _CN10K_ML_DEV_H_ +#include + +/* Marvell OCTEON CN10K ML PMD device name */ +#define MLDEV_NAME_CN10K_PMD ml_cn10k + +/* Device private data */ +struct cn10k_ml_dev { + /* Device ROC */ + struct roc_ml roc; +}; + #endif /* _CN10K_ML_DEV_H_ */ diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c new file mode 100644 index 0000000000..39843e3ee5 --- /dev/null +++ b/drivers/ml/cnxk/cn10k_ml_ops.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2022 Marvell. + */ + +#include +#include + +#include "cn10k_ml_ops.h" + +struct rte_ml_dev_ops cn10k_ml_ops = {0}; diff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h new file mode 100644 index 0000000000..b14221d02c --- /dev/null +++ b/drivers/ml/cnxk/cn10k_ml_ops.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2022 Marvell. + */ + +#ifndef _CN10K_ML_OPS_H_ +#define _CN10K_ML_OPS_H_ + +/* Device ops */ +extern struct rte_ml_dev_ops cn10k_ml_ops; + +#endif /* _CN10K_ML_OPS_H_ */ diff --git a/drivers/ml/cnxk/meson.build b/drivers/ml/cnxk/meson.build index f33fef39e3..aff65a082f 100644 --- a/drivers/ml/cnxk/meson.build +++ b/drivers/ml/cnxk/meson.build @@ -9,10 +9,12 @@ endif driver_sdk_headers = files( 'cn10k_ml_dev.h', + 'cn10k_ml_ops.h', ) sources = files( 'cn10k_ml_dev.c', + 'cn10k_ml_ops.c', ) deps += ['mldev', 'common_ml', 'common_cnxk'] -- 2.17.1