From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 14386A0545; Tue, 20 Dec 2022 20:27:18 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 03D6842D23; Tue, 20 Dec 2022 20:26:59 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id EED5340A7F for ; Tue, 20 Dec 2022 20:26:54 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BKHShum015480 for ; Tue, 20 Dec 2022 11:26:54 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=nRWowxXrv/j/E7IHjvGnHP75t00sN6kQlM76kytHbOo=; b=QZpidV69lscjYN7CbmvU69txhDYpNN3Mx+mN0HBe/SdZzYkxbCJ9gOjhHmj1cyHqWh3+ rsTuc6YrEsvn1bF0zqfQiLy9WiHVp470MF5sz6AYFMWHdCYv1PdGKXUYg5A+ZcKsAqPw T8Dn2R/fSFMFbaVwVe2CAJ2XrkFAd8ZNvVPQpwx53A7c+t1BMI+mzScwhNPDt5W4aK0e ABvam9oTYVjempCqWB0JcMENUCTt4ifMijAJKEf2p/EfmhMd9N5iKETe0AM34BjhFtl3 0cwL/NvmxbO6i2AOslNVL7LSzNOEq6I8jbOaR3Ceq6NNR8kY/Fn4YUPH4pZuEoNj/UtE 7A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3mkapj2tpj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 20 Dec 2022 11:26:53 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 20 Dec 2022 11:26:52 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Tue, 20 Dec 2022 11:26:52 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id C3E083F709D; Tue, 20 Dec 2022 11:26:51 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , Subject: [PATCH v3 04/38] ml/cnxk: add driver support to get device info Date: Tue, 20 Dec 2022 11:26:11 -0800 Message-ID: <20221220192645.14042-5-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221220192645.14042-1-syalavarthi@marvell.com> References: <20221208201806.21893-1-syalavarthi@marvell.com> <20221220192645.14042-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: hwFBVDHA0KpKuJfnXY-M8WvsGfgfkwPL X-Proofpoint-GUID: hwFBVDHA0KpKuJfnXY-M8WvsGfgfkwPL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-20_06,2022-12-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added support to get the cn10k ML device information. This is a driver implementation for the RTE function rte_ml_dev_info_get. ML device on cn10k supports one queue-pair in lock-free mode and does not support segmented input output data. Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_dev.h | 15 +++++++++++++++ drivers/ml/cnxk/cn10k_ml_ops.c | 23 ++++++++++++++++++++++- 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h index 833a09791a..13d26373e4 100644 --- a/drivers/ml/cnxk/cn10k_ml_dev.h +++ b/drivers/ml/cnxk/cn10k_ml_dev.h @@ -10,6 +10,21 @@ /* Marvell OCTEON CN10K ML PMD device name */ #define MLDEV_NAME_CN10K_PMD ml_cn10k +/* Device alignment size */ +#define ML_CN10K_ALIGN_SIZE 128 + +/* Maximum number of models per device */ +#define ML_CN10K_MAX_MODELS 16 + +/* Maximum number of queue-pairs per device */ +#define ML_CN10K_MAX_QP_PER_DEVICE 1 + +/* Maximum number of descriptors per queue-pair */ +#define ML_CN10K_MAX_DESC_PER_QP 1024 + +/* Maximum number of segments for IO data */ +#define ML_CN10K_MAX_SEGMENTS 1 + /* Device private data */ struct cn10k_ml_dev { /* Device ROC */ diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c index 39843e3ee5..bad5ad4713 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.c +++ b/drivers/ml/cnxk/cn10k_ml_ops.c @@ -5,6 +5,27 @@ #include #include +#include "cn10k_ml_dev.h" #include "cn10k_ml_ops.h" -struct rte_ml_dev_ops cn10k_ml_ops = {0}; +static int +cn10k_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info) +{ + if (dev_info == NULL) + return -EINVAL; + + memset(dev_info, 0, sizeof(struct rte_ml_dev_info)); + dev_info->driver_name = dev->device->driver->name; + dev_info->max_models = ML_CN10K_MAX_MODELS; + dev_info->max_queue_pairs = ML_CN10K_MAX_QP_PER_DEVICE; + dev_info->max_desc = ML_CN10K_MAX_DESC_PER_QP; + dev_info->max_segments = ML_CN10K_MAX_SEGMENTS; + dev_info->min_align_size = ML_CN10K_ALIGN_SIZE; + + return 0; +} + +struct rte_ml_dev_ops cn10k_ml_ops = { + /* Device control ops */ + .dev_info_get = cn10k_ml_dev_info_get, +}; -- 2.17.1