From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DC3E9A0093; Fri, 23 Dec 2022 03:52:14 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EEEC042D21; Fri, 23 Dec 2022 03:51:57 +0100 (CET) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id EE85B40685 for ; Fri, 23 Dec 2022 03:51:53 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671763914; x=1703299914; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=H/OfNx7XtGdLPywATEAfIep+22Lkbg/Th0T99YnPF1U=; b=hYgNtOfgYKzt6tuVrc7Aw2wbI3H4aUSX12FhIiiPQUwk+jszUpLiMwTK XyxRywFvQXLceuV47857vR/kVsi9JEsHfMvjUncXPXzdc679M+tZVvl6p i0DLGwJaM18Ke4FEQ1DLhDXEVYaMb76CNPy1EtJoZ8vvCuxYXYk/mH0Tk HCAzf8Dzgwi9NxUoZy6XOje2L9RCh7ktQGs1KJ6M1jlI9InGhss79XX32 GBe2phUSf1YrCJmsOaCzCjIaK/YtNPcir1W1yzKKvVnxa5b0ukIaXlQlB WY1V21BSg8p+7+ENW7oa20o7jK4O5W6vJMyEmnS9G+fy4aDVbTL0NWn9S g==; X-IronPort-AV: E=McAfee;i="6500,9779,10569"; a="321467100" X-IronPort-AV: E=Sophos;i="5.96,267,1665471600"; d="scan'208";a="321467100" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2022 18:51:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10569"; a="629707156" X-IronPort-AV: E=Sophos;i="5.96,267,1665471600"; d="scan'208";a="629707156" Received: from dpdk-mingxial-01.sh.intel.com ([10.67.119.112]) by orsmga006.jf.intel.com with ESMTP; 22 Dec 2022 18:51:51 -0800 From: Mingxia Liu To: dev@dpdk.org Cc: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com, Mingxia Liu Subject: [PATCH 05/21] net/cpfl: support queue start Date: Fri, 23 Dec 2022 01:55:42 +0000 Message-Id: <20221223015558.3143279-6-mingxia.liu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221223015558.3143279-1-mingxia.liu@intel.com> References: <20221223015558.3143279-1-mingxia.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for these device ops: - rx_queue_start - tx_queue_start Signed-off-by: Mingxia Liu --- drivers/net/cpfl/cpfl_ethdev.c | 41 ++++++++++ drivers/net/cpfl/cpfl_rxtx.c | 138 +++++++++++++++++++++++++++++++++ drivers/net/cpfl/cpfl_rxtx.h | 4 + 3 files changed, 183 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index 4c259f24e8..d939dcb005 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -184,6 +184,39 @@ cpfl_dev_configure(struct rte_eth_dev *dev) return 0; } +static int +cpfl_start_queues(struct rte_eth_dev *dev) +{ + struct idpf_rx_queue *rxq; + struct idpf_tx_queue *txq; + int err = 0; + int i; + + for (i = 0; i < dev->data->nb_tx_queues; i++) { + txq = dev->data->tx_queues[i]; + if (txq == NULL || txq->tx_deferred_start) + continue; + err = cpfl_tx_queue_start(dev, i); + if (err != 0) { + PMD_DRV_LOG(ERR, "Fail to start Tx queue %u", i); + return err; + } + } + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + rxq = dev->data->rx_queues[i]; + if (rxq == NULL || rxq->rx_deferred_start) + continue; + err = cpfl_rx_queue_start(dev, i); + if (err != 0) { + PMD_DRV_LOG(ERR, "Fail to start Rx queue %u", i); + return err; + } + } + + return err; +} + static int cpfl_dev_start(struct rte_eth_dev *dev) { @@ -200,6 +233,12 @@ cpfl_dev_start(struct rte_eth_dev *dev) vport->max_pkt_len = dev->data->mtu + CPFL_ETH_OVERHEAD; + ret = cpfl_start_queues(dev); + if (ret != 0) { + PMD_DRV_LOG(ERR, "Failed to start queues"); + goto err_mtu; + } + ret = idpf_vc_ena_dis_vport(vport, true); if (ret != 0) { PMD_DRV_LOG(ERR, "Failed to enable vport"); @@ -584,6 +623,8 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = { .dev_start = cpfl_dev_start, .dev_stop = cpfl_dev_stop, .link_update = cpfl_dev_link_update, + .rx_queue_start = cpfl_rx_queue_start, + .tx_queue_start = cpfl_tx_queue_start, .dev_supported_ptypes_get = cpfl_dev_supported_ptypes_get, }; diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index 695c79e1db..aa67db1e92 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -474,3 +474,141 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, err_txq_alloc: return ret; } + +int +cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id) +{ + struct idpf_rx_queue *rxq; + int err; + + if (rx_queue_id >= dev->data->nb_rx_queues) + return -EINVAL; + + rxq = dev->data->rx_queues[rx_queue_id]; + + if (rxq == NULL || !rxq->q_set) { + PMD_DRV_LOG(ERR, "RX queue %u not available or setup", + rx_queue_id); + return -EINVAL; + } + + if (rxq->bufq1 == NULL) { + /* Single queue */ + err = idpf_alloc_single_rxq_mbufs(rxq); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf"); + return err; + } + + rte_wmb(); + + /* Init the RX tail register. */ + IDPF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1); + } else { + /* Split queue */ + err = idpf_alloc_split_rxq_mbufs(rxq->bufq1); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to allocate RX buffer queue mbuf"); + return err; + } + err = idpf_alloc_split_rxq_mbufs(rxq->bufq2); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to allocate RX buffer queue mbuf"); + return err; + } + + rte_wmb(); + + /* Init the RX tail register. */ + IDPF_PCI_REG_WRITE(rxq->bufq1->qrx_tail, rxq->bufq1->rx_tail); + IDPF_PCI_REG_WRITE(rxq->bufq2->qrx_tail, rxq->bufq2->rx_tail); + } + + return err; +} + +int +cpfl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct idpf_rx_queue *rxq = + dev->data->rx_queues[rx_queue_id]; + int err = 0; + + err = idpf_vc_config_rxq(vport, rxq); + if (err != 0) { + PMD_DRV_LOG(ERR, "Fail to configure Rx queue %u", rx_queue_id); + return err; + } + + err = cpfl_rx_queue_init(dev, rx_queue_id); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to init RX queue %u", + rx_queue_id); + return err; + } + + /* Ready to switch the queue on */ + err = idpf_switch_queue(vport, rx_queue_id, true, true); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on", + rx_queue_id); + } else { + rxq->q_started = true; + dev->data->rx_queue_state[rx_queue_id] = + RTE_ETH_QUEUE_STATE_STARTED; + } + + return err; +} + +int +cpfl_tx_queue_init(struct rte_eth_dev *dev, uint16_t tx_queue_id) +{ + struct idpf_tx_queue *txq; + + if (tx_queue_id >= dev->data->nb_tx_queues) + return -EINVAL; + + txq = dev->data->tx_queues[tx_queue_id]; + + /* Init the RX tail register. */ + IDPF_PCI_REG_WRITE(txq->qtx_tail, 0); + + return 0; +} + +int +cpfl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) +{ + struct idpf_vport *vport = dev->data->dev_private; + struct idpf_tx_queue *txq = + dev->data->tx_queues[tx_queue_id]; + int err = 0; + + err = idpf_vc_config_txq(vport, txq); + if (err != 0) { + PMD_DRV_LOG(ERR, "Fail to configure Tx queue %u", tx_queue_id); + return err; + } + + err = cpfl_tx_queue_init(dev, tx_queue_id); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to init TX queue %u", + tx_queue_id); + return err; + } + + /* Ready to switch the queue on */ + err = idpf_switch_queue(vport, tx_queue_id, false, true); + if (err != 0) { + PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on", + tx_queue_id); + } else { + txq->q_started = true; + dev->data->tx_queue_state[tx_queue_id] = + RTE_ETH_QUEUE_STATE_STARTED; + } + + return err; +} diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h index fd838d3f07..2fa7950775 100644 --- a/drivers/net/cpfl/cpfl_rxtx.h +++ b/drivers/net/cpfl/cpfl_rxtx.h @@ -28,4 +28,8 @@ int cpfl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, uint16_t nb_desc, unsigned int socket_id, const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mp); +int cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id); +int cpfl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); +int cpfl_tx_queue_init(struct rte_eth_dev *dev, uint16_t tx_queue_id); +int cpfl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); #endif /* _CPFL_RXTX_H_ */ -- 2.25.1