From: <skori@marvell.com>
To: Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>
Cc: <dev@dpdk.org>, <stable@dpdk.org>
Subject: [PATCH] common/cnxk: reduce channel count per LMAC
Date: Wed, 4 Jan 2023 11:37:12 +0530 [thread overview]
Message-ID: <20230104060712.283128-1-skori@marvell.com> (raw)
From: Sunil Kumar Kori <skori@marvell.com>
Due to limitation, imposed by latest kernel, maximum number of
channel supported per LMAC is reduced to 8. Because of this change
application gets failed to initialize for more channels.
Also this limitation impacts PFC functional behaviour.
So patch just aligns the supported number of channel with kernel.
Fixes: 20d02329cdc2 ("common/cnxk: support priority flow control")
Cc: stable@dpdk.org
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
---
drivers/common/cnxk/roc_mbox.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 8b0384c737..fd9d3e73cd 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -1169,7 +1169,7 @@ struct nix_bp_cfg_req {
* so maximum 256 channels are possible.
*/
#define NIX_MAX_CHAN 256
-#define NIX_CGX_MAX_CHAN 16
+#define NIX_CGX_MAX_CHAN 8
#define NIX_LBK_MAX_CHAN 1
struct nix_bp_cfg_rsp {
struct mbox_msghdr hdr;
--
2.25.1
next reply other threads:[~2023-01-04 6:07 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-04 6:07 skori [this message]
2023-01-13 5:23 ` Jerin Jacob
2023-01-13 6:29 ` [EXT] " Sunil Kumar Kori
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