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From: Tomasz Duszynski <tduszynski@marvell.com>
To: <dev@dpdk.org>, Tomasz Duszynski <tduszynski@marvell.com>
CC: <thomas@monjalon.net>, <jerinj@marvell.com>, <mb@smartsharesystems.com>,
<Ruifeng.Wang@arm.com>, <mattias.ronnblom@ericsson.com>,
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<roretzla@linux.microsoft.com>
Subject: [PATCH v6 3/4] pmu: support reading Intel x86_64 PMU events in runtime
Date: Fri, 20 Jan 2023 00:39:14 +0100
Message-ID: <20230119233916.4029128-4-tduszynski@marvell.com>
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Add support for reading Intel x86_64 PMU events in runtime.
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
app/test/test_pmu.c | 2 ++
lib/pmu/meson.build | 1 +
lib/pmu/rte_pmu.h | 2 ++
lib/pmu/rte_pmu_pmc_x86_64.h | 24 ++++++++++++++++++++++++
4 files changed, 29 insertions(+)
create mode 100644 lib/pmu/rte_pmu_pmc_x86_64.h
diff --git a/app/test/test_pmu.c b/app/test/test_pmu.c
index 4cdc71791e..dc7a9cdb27 100644
--- a/app/test/test_pmu.c
+++ b/app/test/test_pmu.c
@@ -17,6 +17,8 @@ test_pmu_read(void)
#if defined(RTE_ARCH_ARM64)
event = rte_pmu_add_event("cpu_cycles");
+#elif defined(RTE_ARCH_X86_64)
+ event = rte_pmu_add_event("cpu-cycles");
#endif
while (tries--)
diff --git a/lib/pmu/meson.build b/lib/pmu/meson.build
index e857681137..5b92e5c4e3 100644
--- a/lib/pmu/meson.build
+++ b/lib/pmu/meson.build
@@ -13,6 +13,7 @@ sources = files('rte_pmu.c')
headers = files('rte_pmu.h')
indirect_headers += files(
'rte_pmu_pmc_arm64.h',
+ 'rte_pmu_pmc_x86_64.h',
)
if dpdk_conf.has('RTE_ARCH_ARM64')
diff --git a/lib/pmu/rte_pmu.h b/lib/pmu/rte_pmu.h
index 4808d90eb9..617732361c 100644
--- a/lib/pmu/rte_pmu.h
+++ b/lib/pmu/rte_pmu.h
@@ -28,6 +28,8 @@ extern "C" {
#if defined(RTE_ARCH_ARM64)
#include "rte_pmu_pmc_arm64.h"
+#elif defined(RTE_ARCH_X86_64)
+#include "rte_pmu_pmc_x86_64.h"
#endif
/** Maximum number of events in a group */
diff --git a/lib/pmu/rte_pmu_pmc_x86_64.h b/lib/pmu/rte_pmu_pmc_x86_64.h
new file mode 100644
index 0000000000..7b67466960
--- /dev/null
+++ b/lib/pmu/rte_pmu_pmc_x86_64.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Marvell.
+ */
+#ifndef _RTE_PMU_PMC_X86_64_H_
+#define _RTE_PMU_PMC_X86_64_H_
+
+#include <rte_common.h>
+
+static __rte_always_inline uint64_t
+rte_pmu_pmc_read(int index)
+{
+ uint64_t low, high;
+
+ asm volatile(
+ "rdpmc\n"
+ : "=a" (low), "=d" (high)
+ : "c" (index)
+ );
+
+ return low | (high << 32);
+}
+#define rte_pmu_pmc_read rte_pmu_pmc_read
+
+#endif /* _RTE_PMU_PMC_X86_64_H_ */
--
2.34.1