From: Harshad Narayane <harshad.suresh.narayane@intel.com>
To: dev@dpdk.org
Cc: cristian.dumitrescu@intel.com, harshad.suresh.narayane@intel.com,
kamalakannan.r@intel.com
Subject: [PATCH] pipeline: increase the pipeline instruction table size
Date: Wed, 1 Feb 2023 07:58:57 +0000 [thread overview]
Message-ID: <20230201075857.602848-1-harshad.suresh.narayane@intel.com> (raw)
The complex P4 programs requires more custom instructions, therefore
we increase the pipeline instruction table size from 256 to 1024.
Signed-off-by: Harshad Narayane <harshad.suresh.narayane@intel.com>
Signed-off-by: Kamalakannan R <kamalakannan.r@intel.com>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
---
lib/pipeline/rte_swx_pipeline_internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/pipeline/rte_swx_pipeline_internal.h b/lib/pipeline/rte_swx_pipeline_internal.h
index 335506039b..345b32502c 100644
--- a/lib/pipeline/rte_swx_pipeline_internal.h
+++ b/lib/pipeline/rte_swx_pipeline_internal.h
@@ -1465,7 +1465,7 @@ instr_operand_nbo(struct thread *t, const struct instr_operand *x)
#endif
#ifndef RTE_SWX_PIPELINE_INSTRUCTION_TABLE_SIZE_MAX
-#define RTE_SWX_PIPELINE_INSTRUCTION_TABLE_SIZE_MAX 256
+#define RTE_SWX_PIPELINE_INSTRUCTION_TABLE_SIZE_MAX 1024
#endif
struct rte_swx_pipeline {
--
2.34.1
next reply other threads:[~2023-02-01 8:00 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-01 7:58 Harshad Narayane [this message]
2023-02-06 8:41 ` Thomas Monjalon
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