From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1690741B9D; Wed, 1 Feb 2023 10:25:03 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E4FB842DCC; Wed, 1 Feb 2023 10:23:35 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B379842D48 for ; Wed, 1 Feb 2023 10:23:22 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3116LRXu024189 for ; Wed, 1 Feb 2023 01:23:21 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=6PjhkLuP8CvczEjlMG9M9Ndjl0pelzF953KSxVCkxeg=; b=T6cNT2/WZoXksHV0FP3x2+WBIcPZsL5+OtDGVF2vUZCYDviX0U1DBY7zJ7yXw/4viYd3 QOmTTMwB3UVZavAkzLme8yRi1fndZ8Uf8SFbPJijrHmup9Q1JyfNph0fCmOs5eWHY96p xSNe5rQzBbKOPfuRTToJCUqVWKjq9XFan0V/+KuCFqj+empNFZeZ2VN+0LRIvF+sCBqx QOUc6IdaaCpwwJAM+xrqWNhFyJuuOyZxvhSeHd+A3WStZ1qMwE5uCuCbNR2GtKLubBt1 N/OipXuCmwSBPpjbMQOFyoinH4x4JakNoZKG9ElrNqu8bgwvnzdHhVf2PvVVEnon0Ify Qg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3nfjr8rgv5-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 01 Feb 2023 01:23:21 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 1 Feb 2023 01:23:20 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Wed, 1 Feb 2023 01:23:20 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id 268C95B6922; Wed, 1 Feb 2023 01:23:19 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , Subject: [PATCH v4 20/39] ml/cnxk: enable support to get model information Date: Wed, 1 Feb 2023 01:22:51 -0800 Message-ID: <20230201092310.23252-21-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230201092310.23252-1-syalavarthi@marvell.com> References: <20221208200220.20267-1-syalavarthi@marvell.com> <20230201092310.23252-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: hkwANmlGGV-phgHO-6helvI2LHoLtDJc X-Proofpoint-ORIG-GUID: hkwANmlGGV-phgHO-6helvI2LHoLtDJc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-01_03,2023-01-31_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added driver functions to get model information. Added internal functions to set and get model info. Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_model.c | 55 ++++++++++++++++++++++++++++++++ drivers/ml/cnxk/cn10k_ml_model.h | 9 ++++++ drivers/ml/cnxk/cn10k_ml_ops.c | 37 ++++++++++++++++++--- 3 files changed, 97 insertions(+), 4 deletions(-) diff --git a/drivers/ml/cnxk/cn10k_ml_model.c b/drivers/ml/cnxk/cn10k_ml_model.c index 30911b7ffe..295b6f0a01 100644 --- a/drivers/ml/cnxk/cn10k_ml_model.c +++ b/drivers/ml/cnxk/cn10k_ml_model.c @@ -356,3 +356,58 @@ cn10k_ml_model_ocm_pages_count(struct cn10k_ml_dev *mldev, int16_t model_id, uin return 0; } + +void +cn10k_ml_model_info_set(struct rte_ml_dev *dev, struct cn10k_ml_model *model) +{ + struct rte_ml_model_info *info; + struct rte_ml_io_info *output; + struct rte_ml_io_info *input; + uint8_t i; + + info = PLT_PTR_CAST(model->info); + input = PLT_PTR_ADD(info, sizeof(struct rte_ml_model_info)); + output = + PLT_PTR_ADD(input, model->metadata.model.num_input * sizeof(struct rte_ml_io_info)); + + /* Set model info */ + memset(info, 0, sizeof(struct rte_ml_model_info)); + rte_memcpy(info->name, model->metadata.model.name, MRVL_ML_MODEL_NAME_LEN); + snprintf(info->version, RTE_ML_STR_MAX, "%u.%u.%u.%u", model->metadata.model.version[0], + model->metadata.model.version[1], model->metadata.model.version[2], + model->metadata.model.version[3]); + info->model_id = model->model_id; + info->device_id = dev->data->dev_id; + info->batch_size = model->batch_size; + info->nb_inputs = model->metadata.model.num_input; + info->input_info = input; + info->nb_outputs = model->metadata.model.num_output; + info->output_info = output; + info->wb_size = model->metadata.weights_bias.file_size; + + /* Set input info */ + for (i = 0; i < info->nb_inputs; i++) { + rte_memcpy(input[i].name, model->metadata.input[i].input_name, + MRVL_ML_INPUT_NAME_LEN); + input[i].dtype = model->metadata.input[i].input_type; + input[i].qtype = model->metadata.input[i].model_input_type; + input[i].shape.format = model->metadata.input[i].shape.format; + input[i].shape.w = model->metadata.input[i].shape.w; + input[i].shape.x = model->metadata.input[i].shape.x; + input[i].shape.y = model->metadata.input[i].shape.y; + input[i].shape.z = model->metadata.input[i].shape.z; + } + + /* Set output info */ + for (i = 0; i < info->nb_outputs; i++) { + rte_memcpy(output[i].name, model->metadata.output[i].output_name, + MRVL_ML_OUTPUT_NAME_LEN); + output[i].dtype = model->metadata.output[i].output_type; + output[i].qtype = model->metadata.output[i].model_output_type; + output[i].shape.format = RTE_ML_IO_FORMAT_1D; + output[i].shape.w = model->metadata.output[i].size; + output[i].shape.x = 1; + output[i].shape.y = 1; + output[i].shape.z = 1; + } +} diff --git a/drivers/ml/cnxk/cn10k_ml_model.h b/drivers/ml/cnxk/cn10k_ml_model.h index 003f5aba36..dca282a498 100644 --- a/drivers/ml/cnxk/cn10k_ml_model.h +++ b/drivers/ml/cnxk/cn10k_ml_model.h @@ -422,6 +422,14 @@ struct cn10k_ml_model { /* Tile and memory information object */ struct cn10k_ml_ocm_model_map model_mem_map; + /* Internal model information structure + * Size of the buffer = sizeof(struct rte_ml_model_info) + * + num_inputs * sizeof(struct rte_ml_io_info) + * + num_outputs * sizeof(struct rte_ml_io_info). + * Structures would be arranged in the same order in the buffer. + */ + uint8_t *info; + /* Spinlock, used to update model state */ plt_spinlock_t lock; @@ -438,5 +446,6 @@ void cn10k_ml_model_addr_update(struct cn10k_ml_model *model, uint8_t *buffer, uint8_t *base_dma_addr); int cn10k_ml_model_ocm_pages_count(struct cn10k_ml_dev *mldev, int16_t model_id, uint8_t *buffer, uint16_t *wb_pages, uint16_t *scratch_pages); +void cn10k_ml_model_info_set(struct rte_ml_dev *dev, struct cn10k_ml_model *model); #endif /* _CN10K_ML_MODEL_H_ */ diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c index 295b7794ec..0d6030d36a 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.c +++ b/drivers/ml/cnxk/cn10k_ml_ops.c @@ -506,6 +506,7 @@ cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params, char str[RTE_MEMZONE_NAMESIZE]; const struct plt_memzone *mz; size_t model_data_size; + size_t model_info_size; uint8_t *base_dma_addr; uint16_t scratch_pages; uint16_t wb_pages; @@ -544,8 +545,13 @@ cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params, model_data_size = metadata->init_model.file_size + metadata->main_model.file_size + metadata->finish_model.file_size + metadata->weights_bias.file_size; model_data_size = PLT_ALIGN_CEIL(model_data_size, ML_CN10K_ALIGN_SIZE); + model_info_size = sizeof(struct rte_ml_model_info) + + metadata->model.num_input * sizeof(struct rte_ml_io_info) + + metadata->model.num_output * sizeof(struct rte_ml_io_info); + model_info_size = PLT_ALIGN_CEIL(model_info_size, ML_CN10K_ALIGN_SIZE); + mz_size = PLT_ALIGN_CEIL(sizeof(struct cn10k_ml_model), ML_CN10K_ALIGN_SIZE) + - 2 * model_data_size + + 2 * model_data_size + model_info_size + PLT_ALIGN_CEIL(sizeof(struct cn10k_ml_req), ML_CN10K_ALIGN_SIZE); /* Allocate memzone for model object and model data */ @@ -585,10 +591,12 @@ cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params, model->model_mem_map.wb_pages = wb_pages; model->model_mem_map.scratch_pages = scratch_pages; + /* Set model info */ + model->info = PLT_PTR_ADD(base_dma_addr, 2 * model_data_size); + cn10k_ml_model_info_set(dev, model); + /* Set slow-path request address and state */ - model->req = PLT_PTR_ADD( - mz->addr, PLT_ALIGN_CEIL(sizeof(struct cn10k_ml_model), ML_CN10K_ALIGN_SIZE) + - 2 * model_data_size); + model->req = PLT_PTR_ADD(model->info, model_info_size); plt_spinlock_init(&model->lock); model->state = ML_CN10K_MODEL_STATE_LOADED; @@ -877,6 +885,26 @@ cn10k_ml_model_stop(struct rte_ml_dev *dev, int16_t model_id) return ret; } +static int +cn10k_ml_model_info_get(struct rte_ml_dev *dev, int16_t model_id, + struct rte_ml_model_info *model_info) +{ + struct cn10k_ml_model *model; + + model = dev->data->models[model_id]; + + if (model == NULL) { + plt_err("Invalid model_id = %d", model_id); + return -EINVAL; + } + + rte_memcpy(model_info, model->info, sizeof(struct rte_ml_model_info)); + model_info->input_info = ((struct rte_ml_model_info *)model->info)->input_info; + model_info->output_info = ((struct rte_ml_model_info *)model->info)->output_info; + + return 0; +} + struct rte_ml_dev_ops cn10k_ml_ops = { /* Device control ops */ .dev_info_get = cn10k_ml_dev_info_get, @@ -894,4 +922,5 @@ struct rte_ml_dev_ops cn10k_ml_ops = { .model_unload = cn10k_ml_model_unload, .model_start = cn10k_ml_model_start, .model_stop = cn10k_ml_model_stop, + .model_info_get = cn10k_ml_model_info_get, }; -- 2.17.1