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From: Srikanth Yalavarthi <syalavarthi@marvell.com>
To: Srikanth Yalavarthi <syalavarthi@marvell.com>
CC: <dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,
<aprabhu@marvell.com>
Subject: [PATCH v4 35/39] ml/cnxk: add support to select OCM allocation mode
Date: Wed, 1 Feb 2023 01:23:06 -0800
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Added device argument "ocm_alloc_mode" to select OCM allocation
method during model start. Two modes are supported by the driver.
Added implementation for ocm_alloc_mode lowest as default.
ocm_alloc_mode:
lowest: Allocate from first available free slot / lowest
tile ID in OCM (default)
largest: Allocate from a slot with maximum free memory
Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
---
drivers/ml/cnxk/cn10k_ml_dev.c | 45 +++++++++++++++++++++++++++++-----
drivers/ml/cnxk/cn10k_ml_ocm.c | 6 ++---
drivers/ml/cnxk/cn10k_ml_ocm.h | 3 +++
3 files changed, 44 insertions(+), 10 deletions(-)
diff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c
index 948708a420..5c02d67c8e 100644
--- a/drivers/ml/cnxk/cn10k_ml_dev.c
+++ b/drivers/ml/cnxk/cn10k_ml_dev.c
@@ -21,11 +21,13 @@
#define CN10K_ML_FW_ENABLE_DPE_WARNINGS "enable_dpe_warnings"
#define CN10K_ML_FW_REPORT_DPE_WARNINGS "report_dpe_warnings"
#define CN10K_ML_DEV_CACHE_MODEL_DATA "cache_model_data"
+#define CN10K_ML_OCM_ALLOC_MODE "ocm_alloc_mode"
#define CN10K_ML_FW_PATH_DEFAULT "/lib/firmware/mlip-fw.bin"
#define CN10K_ML_FW_ENABLE_DPE_WARNINGS_DEFAULT 1
#define CN10K_ML_FW_REPORT_DPE_WARNINGS_DEFAULT 0
#define CN10K_ML_DEV_CACHE_MODEL_DATA_DEFAULT 1
+#define CN10K_ML_OCM_ALLOC_MODE_DEFAULT "lowest"
/* ML firmware macros */
#define FW_MEMZONE_NAME "ml_cn10k_fw_mz"
@@ -39,9 +41,12 @@
#define FW_ENABLE_DPE_WARNING_BITMASK BIT(0)
#define FW_REPORT_DPE_WARNING_BITMASK BIT(1)
-static const char *const valid_args[] = {CN10K_ML_FW_PATH, CN10K_ML_FW_ENABLE_DPE_WARNINGS,
+static const char *const valid_args[] = {CN10K_ML_FW_PATH,
+ CN10K_ML_FW_ENABLE_DPE_WARNINGS,
CN10K_ML_FW_REPORT_DPE_WARNINGS,
- CN10K_ML_DEV_CACHE_MODEL_DATA, NULL};
+ CN10K_ML_DEV_CACHE_MODEL_DATA,
+ CN10K_ML_OCM_ALLOC_MODE,
+ NULL};
/* Dummy operations for ML device */
struct rte_ml_dev_ops ml_dev_dummy_ops = {0};
@@ -81,6 +86,8 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde
bool report_dpe_warnings_set = false;
bool cache_model_data_set = false;
struct rte_kvargs *kvlist = NULL;
+ bool ocm_alloc_mode_set = false;
+ char *ocm_alloc_mode = NULL;
bool fw_path_set = false;
char *fw_path = NULL;
int ret = 0;
@@ -140,6 +147,17 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde
cache_model_data_set = true;
}
+ if (rte_kvargs_count(kvlist, CN10K_ML_OCM_ALLOC_MODE) == 1) {
+ ret = rte_kvargs_process(kvlist, CN10K_ML_OCM_ALLOC_MODE, &parse_string_arg,
+ &ocm_alloc_mode);
+ if (ret < 0) {
+ plt_err("Error processing arguments, key = %s\n", CN10K_ML_OCM_ALLOC_MODE);
+ ret = -EINVAL;
+ goto exit;
+ }
+ ocm_alloc_mode_set = true;
+ }
+
check_args:
if (!fw_path_set)
mldev->fw.path = CN10K_ML_FW_PATH_DEFAULT;
@@ -183,6 +201,20 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde
}
plt_info("ML: %s = %d", CN10K_ML_DEV_CACHE_MODEL_DATA, mldev->cache_model_data);
+ if (!ocm_alloc_mode_set) {
+ mldev->ocm.alloc_mode = CN10K_ML_OCM_ALLOC_MODE_DEFAULT;
+ } else {
+ if (!((strcmp(ocm_alloc_mode, "lowest") == 0) ||
+ (strcmp(ocm_alloc_mode, "largest") == 0))) {
+ plt_err("Invalid argument, %s = %s\n", CN10K_ML_OCM_ALLOC_MODE,
+ ocm_alloc_mode);
+ ret = -EINVAL;
+ goto exit;
+ }
+ mldev->ocm.alloc_mode = ocm_alloc_mode;
+ }
+ plt_info("ML: %s = %s", CN10K_ML_OCM_ALLOC_MODE, mldev->ocm.alloc_mode);
+
exit:
if (kvlist)
rte_kvargs_free(kvlist);
@@ -720,7 +752,8 @@ RTE_PMD_REGISTER_PCI(MLDEV_NAME_CN10K_PMD, cn10k_mldev_pmd);
RTE_PMD_REGISTER_PCI_TABLE(MLDEV_NAME_CN10K_PMD, pci_id_ml_table);
RTE_PMD_REGISTER_KMOD_DEP(MLDEV_NAME_CN10K_PMD, "vfio-pci");
-RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD,
- CN10K_ML_FW_PATH "=<path>" CN10K_ML_FW_ENABLE_DPE_WARNINGS
- "=<0|1>" CN10K_ML_FW_REPORT_DPE_WARNINGS
- "=<0|1>" CN10K_ML_DEV_CACHE_MODEL_DATA "=<0|1>");
+RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD, CN10K_ML_FW_PATH
+ "=<path>" CN10K_ML_FW_ENABLE_DPE_WARNINGS
+ "=<0|1>" CN10K_ML_FW_REPORT_DPE_WARNINGS
+ "=<0|1>" CN10K_ML_DEV_CACHE_MODEL_DATA
+ "=<0|1>" CN10K_ML_OCM_ALLOC_MODE "=<lowest|largest>");
diff --git a/drivers/ml/cnxk/cn10k_ml_ocm.c b/drivers/ml/cnxk/cn10k_ml_ocm.c
index 2083d99f81..26e356c107 100644
--- a/drivers/ml/cnxk/cn10k_ml_ocm.c
+++ b/drivers/ml/cnxk/cn10k_ml_ocm.c
@@ -230,7 +230,6 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w
int wb_page_start_curr;
int max_slot_sz_curr;
uint8_t tile_start;
- int ocm_alloc_mode;
int wb_page_start;
uint16_t tile_id;
uint16_t word_id;
@@ -255,7 +254,6 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w
max_slot_sz_curr = 0;
max_slot_sz = 0;
tile_idx = 0;
- ocm_alloc_mode = 2;
if ((start_tile != -1) && (start_tile % num_tiles != 0)) {
plt_err("Invalid start_tile, %d", start_tile);
@@ -303,13 +301,13 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w
}
}
- if (ocm_alloc_mode == 1) {
+ if (strcmp(ocm->alloc_mode, "lowest") == 0) {
wb_page_start = slot_index_lowest(local_ocm_mask, ocm->mask_words, wb_pages, 0);
if (wb_page_start != -1) { /* Have a valid slot for WB, else next set of tiles */
tile_idx = tile_start;
goto found;
}
- } else if (ocm_alloc_mode == 2) {
+ } else if (strcmp(ocm->alloc_mode, "largest") == 0) {
wb_page_start_curr = slot_index_largest(local_ocm_mask, ocm->mask_words, wb_pages,
&max_slot_sz_curr);
if (max_slot_sz_curr > max_slot_sz) {
diff --git a/drivers/ml/cnxk/cn10k_ml_ocm.h b/drivers/ml/cnxk/cn10k_ml_ocm.h
index 4415bbfb45..6bf71c8da6 100644
--- a/drivers/ml/cnxk/cn10k_ml_ocm.h
+++ b/drivers/ml/cnxk/cn10k_ml_ocm.h
@@ -58,6 +58,9 @@ struct cn10k_ml_ocm {
/* OCM spinlock, used to update OCM state */
rte_spinlock_t lock;
+ /* OCM allocation mode */
+ const char *alloc_mode;
+
/* Number of OCM tiles */
uint8_t num_tiles;
--
2.17.1