From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7290441B9D; Wed, 1 Feb 2023 10:24:00 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1302242D69; Wed, 1 Feb 2023 10:23:25 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 2369842BC9 for ; Wed, 1 Feb 2023 10:23:18 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3116M426010261 for ; Wed, 1 Feb 2023 01:23:17 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=99aplHfMZ8leZuIjOnGnatyZ75mxy4/Hjr68DxQZcaM=; b=be/9D7QIxfeC/UY19B4QbtLhMoI+ZANywoP6IfSW85TA5esNhCtIgrbq1jFW2XlrX7k3 kBUZKV4p4w/gXTAlcAYrMN6qkJdDruYY6l71y+tKGDRQmDB9/a8vJPVJMS9OxgJnrati QfVQLnzsemLBQb2/xFcNX7TjCWsAYn6m60387SBxvJ4EaTWYs0r/8XlYoQ4wJSF1wFj5 YqILGV/RcGGUhGRS8XBYJyMuy+O5ZgSeZfhi55hQ/EICt8VYye3CKnBXufusOjOqcAyF E6JvMqTyVybTCU7hev60/h16MI+tMqa395HAQNNjmX4pAWHDr25d3zF9JgayeQQr4zTI qw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nfjrj0s0f-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 01 Feb 2023 01:23:17 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 1 Feb 2023 01:23:15 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Wed, 1 Feb 2023 01:23:15 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id 70F753F70C6; Wed, 1 Feb 2023 01:23:14 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , Subject: [PATCH v4 05/39] ml/cnxk: add support for configure and close Date: Wed, 1 Feb 2023 01:22:36 -0800 Message-ID: <20230201092310.23252-6-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230201092310.23252-1-syalavarthi@marvell.com> References: <20221208200220.20267-1-syalavarthi@marvell.com> <20230201092310.23252-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: 4xyUqBBfHIKyebKbu8yk1E90gaKoPLFj X-Proofpoint-GUID: 4xyUqBBfHIKyebKbu8yk1E90gaKoPLFj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-01_03,2023-01-31_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implemented driver functions to configure and close ML devices. Added skeleton code and support to reconfigure ML device. PCI device remove is enabled in device close. Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_dev.c | 2 ++ drivers/ml/cnxk/cn10k_ml_dev.h | 21 ++++++++++++ drivers/ml/cnxk/cn10k_ml_ops.c | 60 ++++++++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+) diff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c index c2e93c9a1a..fd45226add 100644 --- a/drivers/ml/cnxk/cn10k_ml_dev.c +++ b/drivers/ml/cnxk/cn10k_ml_dev.c @@ -65,6 +65,8 @@ cn10k_ml_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_de dev->dequeue_burst = NULL; dev->op_error_get = NULL; + mldev->state = ML_CN10K_DEV_STATE_PROBED; + return 0; pmd_destroy: diff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h index 13d26373e4..e7fb5fc2e2 100644 --- a/drivers/ml/cnxk/cn10k_ml_dev.h +++ b/drivers/ml/cnxk/cn10k_ml_dev.h @@ -25,10 +25,31 @@ /* Maximum number of segments for IO data */ #define ML_CN10K_MAX_SEGMENTS 1 +/* ML command timeout in seconds */ +#define ML_CN10K_CMD_TIMEOUT 5 + +/* Device configuration state enum */ +enum cn10k_ml_dev_state { + /* Probed and not configured */ + ML_CN10K_DEV_STATE_PROBED = 0, + + /* Configured */ + ML_CN10K_DEV_STATE_CONFIGURED, + + /* Started */ + ML_CN10K_DEV_STATE_STARTED, + + /* Closed */ + ML_CN10K_DEV_STATE_CLOSED +}; + /* Device private data */ struct cn10k_ml_dev { /* Device ROC */ struct roc_ml roc; + + /* Configuration state */ + enum cn10k_ml_dev_state state; }; #endif /* _CN10K_ML_DEV_H_ */ diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c index bad5ad4713..32d38569a3 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.c +++ b/drivers/ml/cnxk/cn10k_ml_ops.c @@ -25,7 +25,67 @@ cn10k_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info) return 0; } +static int +cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *conf) +{ + struct rte_ml_dev_info dev_info; + struct cn10k_ml_dev *mldev; + + if (dev == NULL || conf == NULL) + return -EINVAL; + + /* Get CN10K device handle */ + mldev = dev->data->dev_private; + + cn10k_ml_dev_info_get(dev, &dev_info); + if (conf->nb_models > dev_info.max_models) { + plt_err("Invalid device config, nb_models > %d\n", dev_info.max_models); + return -EINVAL; + } + + if (conf->nb_queue_pairs > dev_info.max_queue_pairs) { + plt_err("Invalid device config, nb_queue_pairs > %u\n", dev_info.max_queue_pairs); + return -EINVAL; + } + + if (mldev->state == ML_CN10K_DEV_STATE_PROBED) { + plt_ml_dbg("Configuring ML device, nb_queue_pairs = %u, nb_models = %u", + conf->nb_queue_pairs, conf->nb_models); + } else if (mldev->state == ML_CN10K_DEV_STATE_CONFIGURED) { + plt_ml_dbg("Re-configuring ML device, nb_queue_pairs = %u, nb_models = %u", + conf->nb_queue_pairs, conf->nb_models); + } else if (mldev->state == ML_CN10K_DEV_STATE_STARTED) { + plt_err("Device can't be reconfigured in started state\n"); + return -ENOTSUP; + } else if (mldev->state == ML_CN10K_DEV_STATE_CLOSED) { + plt_err("Device can't be reconfigured after close\n"); + return -ENOTSUP; + } + + mldev->state = ML_CN10K_DEV_STATE_CONFIGURED; + + return 0; +} + +static int +cn10k_ml_dev_close(struct rte_ml_dev *dev) +{ + struct cn10k_ml_dev *mldev; + + if (dev == NULL) + return -EINVAL; + + mldev = dev->data->dev_private; + + mldev->state = ML_CN10K_DEV_STATE_CLOSED; + + /* Remove PCI device */ + return rte_dev_remove(dev->device); +} + struct rte_ml_dev_ops cn10k_ml_ops = { /* Device control ops */ .dev_info_get = cn10k_ml_dev_info_get, + .dev_configure = cn10k_ml_dev_configure, + .dev_close = cn10k_ml_dev_close, }; -- 2.17.1