From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3B90141B9D; Wed, 1 Feb 2023 10:24:27 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2686D42D88; Wed, 1 Feb 2023 10:23:29 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 3195142D29 for ; Wed, 1 Feb 2023 10:23:19 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3116M428010261 for ; Wed, 1 Feb 2023 01:23:18 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=UxghtxWNIoa/urab9LWIQBwNFxc60gxPtTINtsrmkoM=; b=QwtlM92gKF9V1iOuBKRP6XWHtC1f/fC70/gHiMFaR6C/Enm13KdmmfMaprGFGwMyWUB3 FXyw2bz6eVWI1I3vdUXFe5BKhgcHJqbuE6mdCd0MAciuVq42qcvFwspMjjg8MhjO2fl7 4dseissM85ruUZlgmFYuXUBdxsKzWxO05FxJjjKcQbNvQkc3DoU2boL65y//meh4SwGC 0jPdQIFIAA69lfsGDh35QlqmkI3AWhFHKP3vvHgf7XcG01ugiPs4AvxKF6MBogX6TyLU eI619y4Eh3dgydxvyHpHIOJDrgovqZg4xSkvk3bOTeWOdRV5q43HrpdKYxreBHzhf++W yw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nfjrj0s0f-5 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 01 Feb 2023 01:23:18 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 1 Feb 2023 01:23:16 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Wed, 1 Feb 2023 01:23:15 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id 5EFA63F70E7; Wed, 1 Feb 2023 01:23:15 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , Subject: [PATCH v4 08/39] ml/cnxk: enable support for simulator environment Date: Wed, 1 Feb 2023 01:22:39 -0800 Message-ID: <20230201092310.23252-9-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230201092310.23252-1-syalavarthi@marvell.com> References: <20221208200220.20267-1-syalavarthi@marvell.com> <20230201092310.23252-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: -anLdFDDd00uv6LSPKPW8E66Sv2BujMg X-Proofpoint-GUID: -anLdFDDd00uv6LSPKPW8E66Sv2BujMg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-01_03,2023-01-31_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enabled device initialization and firmware load on simulator platform. Firmware load stage on simulator would involve launching a firmware handshake request only. Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_dev.c | 119 +++++++++++++++++++++++++++++---- 1 file changed, 107 insertions(+), 12 deletions(-) diff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c index 90fca45ddd..837f006bf0 100644 --- a/drivers/ml/cnxk/cn10k_ml_dev.c +++ b/drivers/ml/cnxk/cn10k_ml_dev.c @@ -213,6 +213,89 @@ cn10k_ml_fw_flags_get(struct cn10k_ml_fw *fw) return FW_LOAD_FLAGS; } +static int +cn10k_ml_fw_load_asim(struct cn10k_ml_fw *fw) +{ + struct cn10k_ml_dev *mldev; + uint64_t timeout_cycle; + uint64_t reg_val64; + bool timeout; + int ret = 0; + + mldev = fw->mldev; + + /* Reset HEAD and TAIL debug pointer registers */ + roc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_DBG_BUFFER_HEAD_C0); + roc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_DBG_BUFFER_TAIL_C0); + roc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_DBG_BUFFER_HEAD_C1); + roc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_DBG_BUFFER_TAIL_C1); + roc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_EXCEPTION_SP_C0); + roc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_EXCEPTION_SP_C1); + + /* Set ML_MLR_BASE to base IOVA of the ML region in LLC/DRAM. */ + reg_val64 = rte_eal_get_baseaddr(); + roc_ml_reg_write64(&mldev->roc, reg_val64, ML_MLR_BASE); + plt_ml_dbg("ML_MLR_BASE = 0x%016lx", roc_ml_reg_read64(&mldev->roc, ML_MLR_BASE)); + roc_ml_reg_save(&mldev->roc, ML_MLR_BASE); + + /* Update FW load completion structure */ + fw->req->jd.hdr.jce.w1.u64 = PLT_U64_CAST(&fw->req->status); + fw->req->jd.hdr.job_type = ML_CN10K_JOB_TYPE_FIRMWARE_LOAD; + fw->req->jd.hdr.result = roc_ml_addr_ap2mlip(&mldev->roc, &fw->req->result); + fw->req->jd.fw_load.flags = cn10k_ml_fw_flags_get(fw); + plt_write64(ML_CN10K_POLL_JOB_START, &fw->req->status); + plt_wmb(); + + /* Enqueue FW load through scratch registers */ + timeout = true; + timeout_cycle = plt_tsc_cycles() + ML_CN10K_CMD_TIMEOUT * plt_tsc_hz(); + roc_ml_scratch_enqueue(&mldev->roc, &fw->req->jd); + + plt_rmb(); + do { + if (roc_ml_scratch_is_done_bit_set(&mldev->roc) && + (plt_read64(&fw->req->status) == ML_CN10K_POLL_JOB_FINISH)) { + timeout = false; + break; + } + } while (plt_tsc_cycles() < timeout_cycle); + + /* Check firmware load status, clean-up and exit on failure. */ + if ((!timeout) && (fw->req->result.error_code == 0)) { + cn10k_ml_fw_print_info(fw); + } else { + /* Set ML to disable new jobs */ + reg_val64 = (ROC_ML_CFG_JD_SIZE | ROC_ML_CFG_MLIP_ENA); + roc_ml_reg_write64(&mldev->roc, reg_val64, ML_CFG); + + /* Clear scratch registers */ + roc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_WORK_PTR); + roc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_FW_CTRL); + + if (timeout) { + plt_err("Firmware load timeout"); + ret = -ETIME; + } else { + plt_err("Firmware load failed"); + ret = -1; + } + + return ret; + } + + /* Reset scratch registers */ + roc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_FW_CTRL); + roc_ml_reg_write64(&mldev->roc, 0, ML_SCRATCH_WORK_PTR); + + /* Disable job execution, to be enabled in start */ + reg_val64 = roc_ml_reg_read64(&mldev->roc, ML_CFG); + reg_val64 &= ~ROC_ML_CFG_ENA; + roc_ml_reg_write64(&mldev->roc, reg_val64, ML_CFG); + plt_ml_dbg("ML_CFG => 0x%016lx", roc_ml_reg_read64(&mldev->roc, ML_CFG)); + + return ret; +} + static int cn10k_ml_fw_load_cn10ka(struct cn10k_ml_fw *fw, void *buffer, uint64_t size) { @@ -447,16 +530,22 @@ cn10k_ml_fw_load(struct cn10k_ml_dev *mldev) fw = &mldev->fw; fw->mldev = mldev; - /* Read firmware image to a buffer */ - ret = rte_firmware_read(fw->path, &fw_buffer, &fw_size); - if (ret < 0) { - plt_err("Can't read firmware data: %s\n", fw->path); - return ret; + if (roc_env_is_emulator() || roc_env_is_hw()) { + /* Read firmware image to a buffer */ + ret = rte_firmware_read(fw->path, &fw_buffer, &fw_size); + if (ret < 0) { + plt_err("Can't read firmware data: %s\n", fw->path); + return ret; + } + + /* Reserve memzone for firmware load completion and data */ + mz_size = sizeof(struct cn10k_ml_req) + fw_size + FW_STACK_BUFFER_SIZE + + FW_DEBUG_BUFFER_SIZE + FW_EXCEPTION_BUFFER_SIZE; + } else if (roc_env_is_asim()) { + /* Reserve memzone for firmware load completion */ + mz_size = sizeof(struct cn10k_ml_req); } - /* Reserve memzone for firmware load completion and data */ - mz_size = sizeof(struct cn10k_ml_req) + fw_size + FW_STACK_BUFFER_SIZE + - FW_DEBUG_BUFFER_SIZE + FW_EXCEPTION_BUFFER_SIZE; mz = plt_memzone_reserve_aligned(FW_MEMZONE_NAME, mz_size, 0, ML_CN10K_ALIGN_SIZE); if (mz == NULL) { plt_err("plt_memzone_reserve failed : %s", FW_MEMZONE_NAME); @@ -475,10 +564,16 @@ cn10k_ml_fw_load(struct cn10k_ml_dev *mldev) roc_ml_mlip_reset(&mldev->roc, true); /* Load firmware */ - fw->data = PLT_PTR_ADD(mz->addr, sizeof(struct cn10k_ml_req)); - ret = cn10k_ml_fw_load_cn10ka(fw, fw_buffer, fw_size); - if (fw_buffer != NULL) - free(fw_buffer); + if (roc_env_is_emulator() || roc_env_is_hw()) { + fw->data = PLT_PTR_ADD(mz->addr, sizeof(struct cn10k_ml_req)); + ret = cn10k_ml_fw_load_cn10ka(fw, fw_buffer, fw_size); + if (fw_buffer != NULL) + free(fw_buffer); + } else if (roc_env_is_asim()) { + fw->data = NULL; + ret = cn10k_ml_fw_load_asim(fw); + } + if (ret < 0) cn10k_ml_fw_unload(mldev); -- 2.17.1