From: Jiawei Wang <jiaweiw@nvidia.com>
To: <viacheslavo@nvidia.com>, <orika@nvidia.com>,
Matan Azrad <matan@nvidia.com>
Cc: <dev@dpdk.org>, <rasland@nvidia.com>
Subject: [PATCH 1/3] drivers: add lag Rx port affinity in PRM
Date: Fri, 3 Feb 2023 07:21:05 +0200 [thread overview]
Message-ID: <20230203052107.48293-2-jiaweiw@nvidia.com> (raw)
In-Reply-To: <20230203052107.48293-1-jiaweiw@nvidia.com>
This patch adds function to query hca capability via Devx for
lag_rx_port_affinity.
Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++
drivers/common/mlx5/mlx5_devx_cmds.h | 1 +
drivers/common/mlx5/mlx5_prm.h | 7 +++++--
drivers/net/mlx5/linux/mlx5_os.c | 4 ++++
drivers/net/mlx5/mlx5.h | 2 ++
5 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index e3a4927d0f..a157ab4b6c 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1141,6 +1141,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
attr->outer_ipv4_ihl = MLX5_GET
(flow_table_nic_cap, hcattr,
ft_field_support_2_nic_receive.outer_ipv4_ihl);
+ attr->lag_rx_port_affinity = MLX5_GET
+ (flow_table_nic_cap, hcattr,
+ ft_field_support_2_nic_receive.lag_rx_port_affinity);
/* Query HCA offloads for Ethernet protocol. */
hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index c94b9eac06..9cf045ccaa 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -288,6 +288,7 @@ struct mlx5_hca_attr {
uint32_t alloc_flow_counter_pd:1;
uint32_t flow_counter_access_aso:1;
uint32_t flow_access_aso_opc_mod:8;
+ uint32_t lag_rx_port_affinity:1;
};
/* LAG Context. */
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 9294f65e24..8bbb800206 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -905,7 +905,8 @@ struct mlx5_ifc_fte_match_set_misc_bits {
u8 vxlan_vni[0x18];
u8 reserved_at_b8[0x8];
u8 geneve_vni[0x18];
- u8 reserved_at_e4[0x6];
+ u8 lag_rx_port_affinity[0x4];
+ u8 reserved_at_e8[0x2];
u8 geneve_tlv_option_0_exist[0x1];
u8 geneve_oam[0x1];
u8 reserved_at_e0[0xc];
@@ -2044,7 +2045,9 @@ struct mlx5_ifc_ft_fields_support_bits {
* Table 1872 - Flow Table Fields Supported 2 Format
*/
struct mlx5_ifc_ft_fields_support_2_bits {
- u8 reserved_at_0[0xd];
+ u8 reserved_at_0[0xa];
+ u8 lag_rx_port_affinity[0x1];
+ u8 reserved_at_c[0x2];
u8 hash_result[0x1];
u8 reserved_at_e[0x1];
u8 tunnel_header_2_3[0x1];
diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index a71474c90a..60462da39d 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -1390,6 +1390,10 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
DRV_LOG(DEBUG, "DV flow is not supported!");
}
#endif
+ if (hca_attr->lag_rx_port_affinity) {
+ sh->lag_rx_port_affinity_en = 1;
+ DRV_LOG(DEBUG, "LAG Rx Port Affinity enabled");
+ }
}
/* Process parameters and store port configuration on priv structure. */
err = mlx5_port_args_config(priv, mkvlist, &priv->config);
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 16b33e1548..bbd7262a51 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1374,6 +1374,8 @@ struct mlx5_dev_ctx_shared {
uint32_t hws_tags:1; /* Check if tags info for HWS initialized. */
uint32_t shared_mark_enabled:1;
/* If mark action is enabled on Rxqs (shared E-Switch domain). */
+ uint32_t lag_rx_port_affinity_en:1;
+ /* lag_rx_port_affinity is supported. */
uint32_t hws_max_log_bulk_sz:5;
/* Log of minimal HWS counters created hard coded. */
uint32_t hws_max_nb_counters; /* Maximal number for HWS counters. */
--
2.18.1
next prev parent reply other threads:[~2023-02-03 5:21 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-03 5:21 [PATCH 0/3] add new PHY affinity support in MLX5 PMD Jiawei Wang
2023-02-03 5:21 ` Jiawei Wang [this message]
2023-02-03 5:21 ` [PATCH 2/3] net/mlx5: add PHY affinity item support Jiawei Wang
2023-02-03 5:21 ` [PATCH 3/3] drivers: enhance the Tx queue affinity Jiawei Wang
2023-02-22 12:26 ` [PATCH v2 0/3] Add Tx queue mapping of aggregated ports in MLX5 PMD Jiawei Wang
2023-02-22 12:26 ` [PATCH v2 1/3] net/mlx5: add lag Rx port affinity in PRM Jiawei Wang
2023-02-22 12:26 ` [PATCH v2 2/3] net/mlx5: add aggregated affinity item support Jiawei Wang
2023-02-22 12:26 ` [PATCH v2 3/3] net/mlx5: enhance the Tx queue affinity Jiawei Wang
2023-02-26 14:35 ` [PATCH v2 0/3] Add Tx queue mapping of aggregated ports in MLX5 PMD Raslan Darawsheh
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230203052107.48293-2-jiaweiw@nvidia.com \
--to=jiaweiw@nvidia.com \
--cc=dev@dpdk.org \
--cc=matan@nvidia.com \
--cc=orika@nvidia.com \
--cc=rasland@nvidia.com \
--cc=viacheslavo@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).