From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 83D1841BBB; Fri, 3 Feb 2023 11:06:16 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6845942D32; Fri, 3 Feb 2023 11:06:05 +0100 (CET) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 4701B42D2F for ; Fri, 3 Feb 2023 11:06:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675418763; x=1706954763; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o/sqCiW8vydt3bQaRwXMR1/1WREbyJBdFP1cTgrpLTw=; b=kX0nOAIs8L2Tcw2b7adD2VQpZo+/CZMI+Vj6jfygYNIgi8bEUlRUOi/p 7pIKM0dsNB4wGpLK+OvvyAZmvRcAscid/0yfE1q0tJ8nKnkNZZqaV22bf 3lJKilAhTUHnrZy+dh4Jbcfmo4hEpBjaaLyeie4Td0MHgsLYXPQzLGTvE Cjd8dAbX5haeKBboBoJhWfGDiDcodZELq/R5WozLU2wohuKQLT2ChPto3 nvokPtc53RTY2k+nH89/QRnK1qNbKjZIZeQpWLjy2chAnDCWF1unrOCq3 iUYjx/GBBfhZqjcBecXk+kYd7/7riI4lJo1KdBxzOFYiMyY8bMqoad9Bx g==; X-IronPort-AV: E=McAfee;i="6500,9779,10609"; a="316705062" X-IronPort-AV: E=Sophos;i="5.97,270,1669104000"; d="scan'208";a="316705062" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2023 02:06:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10609"; a="994465520" X-IronPort-AV: E=Sophos;i="5.97,270,1669104000"; d="scan'208";a="994465520" Received: from silpixa00401385.ir.intel.com ([10.237.214.158]) by fmsmga005.fm.intel.com with ESMTP; 03 Feb 2023 02:06:01 -0800 From: Bruce Richardson To: dev@dpdk.org Cc: jasvinder.singh@intel.com, Bruce Richardson , Cristian Dumitrescu Subject: [PATCH 4/4] examples/qos_sched: remove limit on core ids Date: Fri, 3 Feb 2023 10:05:33 +0000 Message-Id: <20230203100533.10377-5-bruce.richardson@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230203100533.10377-1-bruce.richardson@intel.com> References: <20230203100533.10377-1-bruce.richardson@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The qos_sched app was limited to using lcores between 0 and 64 only, even if RTE_MAX_LCORE was set to a higher value (as it is by default). Remove some of the checks on the lcore ids in order to support running with core ids > 64. Signed-off-by: Bruce Richardson --- examples/qos_sched/args.c | 72 ++------------------------------------- examples/qos_sched/main.h | 10 +----- 2 files changed, 4 insertions(+), 78 deletions(-) diff --git a/examples/qos_sched/args.c b/examples/qos_sched/args.c index b2959499ae..e97273152a 100644 --- a/examples/qos_sched/args.c +++ b/examples/qos_sched/args.c @@ -24,7 +24,6 @@ static uint32_t app_main_core = 1; static uint32_t app_numa_mask; -static uint64_t app_used_core_mask = 0; static uint64_t app_used_port_mask = 0; static uint64_t app_used_rx_port_mask = 0; static uint64_t app_used_tx_port_mask = 0; @@ -82,43 +81,6 @@ app_usage(const char *prgname) } -/* returns core mask used by DPDK */ -static uint64_t -app_eal_core_mask(void) -{ - uint64_t cm = 0; - uint32_t i; - - for (i = 0; i < APP_MAX_LCORE; i++) { - if (rte_lcore_has_role(i, ROLE_RTE)) - cm |= (1ULL << i); - } - - cm |= (1ULL << rte_get_main_lcore()); - - return cm; -} - - -/* returns total number of cores presented in a system */ -static uint32_t -app_cpu_core_count(void) -{ - int i, len; - char path[PATH_MAX]; - uint32_t ncores = 0; - - for (i = 0; i < APP_MAX_LCORE; i++) { - len = snprintf(path, sizeof(path), SYS_CPU_DIR, i); - if (len <= 0 || (unsigned)len >= sizeof(path)) - continue; - - if (access(path, F_OK) == 0) - ncores++; - } - - return ncores; -} /* returns: number of values parsed @@ -261,15 +223,6 @@ app_parse_flow_conf(const char *conf_str) app_used_tx_port_mask |= mask; app_used_port_mask |= mask; - mask = 1lu << pconf->rx_core; - app_used_core_mask |= mask; - - mask = 1lu << pconf->wt_core; - app_used_core_mask |= mask; - - mask = 1lu << pconf->tx_core; - app_used_core_mask |= mask; - nb_pfc++; return 0; @@ -322,7 +275,7 @@ app_parse_args(int argc, char **argv) int opt, ret; int option_index; char *prgname = argv[0]; - uint32_t i, nb_lcores; + uint32_t i; static struct option lgopts[] = { {OPT_PFC, 1, NULL, OPT_PFC_NUM}, @@ -425,23 +378,6 @@ app_parse_args(int argc, char **argv) } } - /* check main core index validity */ - for (i = 0; i <= app_main_core; i++) { - if (app_used_core_mask & RTE_BIT64(app_main_core)) { - RTE_LOG(ERR, APP, "Main core index is not configured properly\n"); - app_usage(prgname); - return -1; - } - } - app_used_core_mask |= RTE_BIT64(app_main_core); - - if ((app_used_core_mask != app_eal_core_mask()) || - (app_main_core != rte_get_main_lcore())) { - RTE_LOG(ERR, APP, "EAL core mask not configured properly, must be %" PRIx64 - " instead of %" PRIx64 "\n" , app_used_core_mask, app_eal_core_mask()); - return -1; - } - if (nb_pfc == 0) { RTE_LOG(ERR, APP, "Packet flow not configured!\n"); app_usage(prgname); @@ -449,15 +385,13 @@ app_parse_args(int argc, char **argv) } /* sanity check for cores assignment */ - nb_lcores = app_cpu_core_count(); - for(i = 0; i < nb_pfc; i++) { - if (qos_conf[i].rx_core >= nb_lcores) { + if (qos_conf[i].rx_core >= RTE_MAX_LCORE) { RTE_LOG(ERR, APP, "pfc %u: invalid RX lcore index %u\n", i + 1, qos_conf[i].rx_core); return -1; } - if (qos_conf[i].wt_core >= nb_lcores) { + if (qos_conf[i].wt_core >= RTE_MAX_LCORE) { RTE_LOG(ERR, APP, "pfc %u: invalid WT lcore index %u\n", i + 1, qos_conf[i].wt_core); return -1; diff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h index d8f3e32c83..bc647ec595 100644 --- a/examples/qos_sched/main.h +++ b/examples/qos_sched/main.h @@ -37,15 +37,7 @@ extern "C" { #define TX_HTHRESH 0 /**< Default values of TX host threshold reg. */ #define TX_WTHRESH 0 /**< Default values of TX write-back threshold reg. */ -#ifndef APP_MAX_LCORE -#if (RTE_MAX_LCORE > 64) -#define APP_MAX_LCORE 64 -#else -#define APP_MAX_LCORE RTE_MAX_LCORE -#endif -#endif - -#define MAX_DATA_STREAMS (APP_MAX_LCORE/2) +#define MAX_DATA_STREAMS RTE_MAX_LCORE/2 #define MAX_SCHED_SUBPORTS 8 #define MAX_SCHED_PIPES 4096 #define MAX_SCHED_PIPE_PROFILES 256 -- 2.37.2