From: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
To: <dev@dpdk.org>
Cc: <matan@nvidia.com>, <rasland@nvidia.com>, <orika@nvidia.com>,
"Hamdan Igbaria" <hamdani@nvidia.com>
Subject: [PATCH] net/mlx5/hws: support match on ESP item
Date: Mon, 6 Feb 2023 11:55:50 +0200 [thread overview]
Message-ID: <20230206095550.24572-1-viacheslavo@nvidia.com> (raw)
From: Hamdan Igbaria <hamdani@nvidia.com>
Add the support to match on SPI and sequence
number fields of ESP header.
The match on ESP header in harwdare steering
is supported only if firmware reports the device
supports IPsec offload.
Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
drivers/common/mlx5/mlx5_prm.h | 3 ++-
drivers/net/mlx5/hws/mlx5dr_cmd.c | 3 +++
drivers/net/mlx5/hws/mlx5dr_cmd.h | 1 +
drivers/net/mlx5/hws/mlx5dr_definer.c | 38 ++++++++++++++++++++++++++-
drivers/net/mlx5/hws/mlx5dr_definer.h | 2 ++
drivers/net/mlx5/mlx5_flow_hw.c | 1 +
6 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 9294f65e24..0ee4b575d4 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -1695,7 +1695,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_460[0x8];
u8 aes_xts[0x1];
u8 crypto[0x1];
- u8 reserved_at_46a[0x6];
+ u8 ipsec_offload[0x1];
+ u8 reserved_at_46b[0x5];
u8 max_num_eqs[0x10];
u8 reserved_at_480[0x3];
u8 log_max_l2_table[0x5];
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c
index 32378673cf..c60da381b2 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c
@@ -850,6 +850,9 @@ int mlx5dr_cmd_query_caps(struct ibv_context *ctx,
caps->sq_ts_format = MLX5_GET(query_hca_cap_out, out,
capability.cmd_hca_cap.sq_ts_format);
+ caps->ipsec_offload = MLX5_GET(query_hca_cap_out, out,
+ capability.cmd_hca_cap.ipsec_offload);
+
MLX5_SET(query_hca_cap_in, in, op_mod,
MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
MLX5_HCA_CAP_OPMOD_GET_CUR);
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h
index 468557ba16..af779e4bcd 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h
@@ -188,6 +188,7 @@ struct mlx5dr_cmd_query_caps {
bool cross_vhca_resources;
uint32_t shared_vhca_id;
char fw_ver[64];
+ bool ipsec_offload;
};
int mlx5dr_cmd_destroy_obj(struct mlx5dr_devx_obj *devx_obj);
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 6b98eb8c96..ab65409629 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -162,7 +162,9 @@ struct mlx5dr_definer_conv_data {
X(SET_BE32, gre_opt_key, v->key.key, rte_flow_item_gre_opt) \
X(SET_BE32, gre_opt_seq, v->sequence.sequence, rte_flow_item_gre_opt) \
X(SET_BE16, gre_opt_checksum, v->checksum_rsvd.checksum, rte_flow_item_gre_opt) \
- X(SET, meter_color, rte_col_2_mlx5_col(v->color), rte_flow_item_meter_color)
+ X(SET, meter_color, rte_col_2_mlx5_col(v->color), rte_flow_item_meter_color) \
+ X(SET_BE32, ipsec_spi, v->hdr.spi, rte_flow_item_esp) \
+ X(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp)
/* Item set function format */
#define X(set_type, func_name, value, item_type) \
@@ -1465,6 +1467,36 @@ mlx5dr_definer_conv_item_meter_color(struct mlx5dr_definer_conv_data *cd,
return 0;
}
+static int
+mlx5dr_definer_conv_item_esp(struct mlx5dr_definer_conv_data *cd,
+ struct rte_flow_item *item,
+ int item_idx)
+{
+ const struct rte_flow_item_esp *m = item->mask;
+ struct mlx5dr_definer_fc *fc;
+
+ if (!cd->caps->ipsec_offload) {
+ rte_errno = ENOTSUP;
+ return rte_errno;
+ }
+
+ if (!m)
+ return 0;
+ if (m->hdr.spi) {
+ fc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SPI];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_ipsec_spi_set;
+ DR_CALC_SET_HDR(fc, ipsec, spi);
+ }
+ if (m->hdr.seq) {
+ fc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_ipsec_sequence_number_set;
+ DR_CALC_SET_HDR(fc, ipsec, sequence_number);
+ }
+ return 0;
+}
+
static int
mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
struct mlx5dr_match_template *mt,
@@ -1581,6 +1613,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
ret = mlx5dr_definer_conv_item_meter_color(&cd, items, i);
item_flags |= MLX5_FLOW_ITEM_METER_COLOR;
break;
+ case RTE_FLOW_ITEM_TYPE_ESP:
+ ret = mlx5dr_definer_conv_item_esp(&cd, items, i);
+ item_flags |= MLX5_FLOW_ITEM_ESP;
+ break;
default:
DR_LOG(ERR, "Unsupported item type %d", items->type);
rte_errno = ENOTSUP;
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index d52c6b0627..d0ecbe9325 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -106,6 +106,8 @@ enum mlx5dr_definer_fname {
MLX5DR_DEFINER_FNAME_INTEGRITY_I,
MLX5DR_DEFINER_FNAME_ICMP_DW1,
MLX5DR_DEFINER_FNAME_ICMP_DW2,
+ MLX5DR_DEFINER_FNAME_ESP_SPI,
+ MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER,
MLX5DR_DEFINER_FNAME_MAX,
};
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 20c71ff7f0..ce9e0219e1 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -4732,6 +4732,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,
case RTE_FLOW_ITEM_TYPE_ICMP:
case RTE_FLOW_ITEM_TYPE_ICMP6:
case RTE_FLOW_ITEM_TYPE_CONNTRACK:
+ case RTE_FLOW_ITEM_TYPE_ESP:
break;
case RTE_FLOW_ITEM_TYPE_INTEGRITY:
/*
--
2.18.1
next reply other threads:[~2023-02-06 9:56 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 9:55 Viacheslav Ovsiienko [this message]
2023-02-07 11:40 ` [PATCH v2] " Viacheslav Ovsiienko
2023-02-07 13:56 ` [PATCH v2] doc: update cross-port indirect shared action Viacheslav Ovsiienko
2023-02-13 13:45 ` [PATCH v3] net/mlx5/hws: support match on ESP item Viacheslav Ovsiienko
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