From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4E7DB41C30; Tue, 7 Feb 2023 17:10:38 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 243C742FB0; Tue, 7 Feb 2023 17:07:55 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 26A3042D40 for ; Tue, 7 Feb 2023 17:07:33 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 317EgVTu017206 for ; Tue, 7 Feb 2023 08:07:32 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=Ar2vR9cjXlqN28pPjqE706UZSMuZZm0oXKz9QCaUprI=; b=ZzlTHn1CIbyF6KkG2dl9B9K9qfuYUgsnzW/dZzveIm7typJ7jpy4Q02qBywZh2XwtIUw Gt2XGQYoqBaYAdVQITnPjOLiuYMgSiK4OuIqL0Mhyk9wotqk1k8TfUUyrSIq+J3MnEsx QPxC8cssT6f7LLaJ/As7uz8zAbXJmWmTyYVyMu/ez7S+ButfR6v0rAZzUAZWKyZN1CS3 5IoLXkzS9J0Kaa2v4uJjNAZwNW+Nt59aIks6zJ87M3cWDMWHoSKZ+W5Rmh1DoM8+x6Jb bEKoHvCqTPZ5dgQFaQbZo15fkAylatxkKVD+rGhJdqnGQILUhXorFGWXzImpMMYs4bnr Iw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3nkdyrssx7-15 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 07 Feb 2023 08:07:32 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 7 Feb 2023 08:07:29 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Tue, 7 Feb 2023 08:07:29 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id E1F133F7085; Tue, 7 Feb 2023 08:07:28 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , , , Subject: [PATCH v5 25/39] ml/cnxk: add driver support for device selftest Date: Tue, 7 Feb 2023 08:07:05 -0800 Message-ID: <20230207160719.1307-26-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230207160719.1307-1-syalavarthi@marvell.com> References: <20221208200220.20267-1-syalavarthi@marvell.com> <20230207160719.1307-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: NMjLbEcNxiBhKfZKRypgUstJYmN1tErV X-Proofpoint-GUID: NMjLbEcNxiBhKfZKRypgUstJYmN1tErV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-07_07,2023-02-06_03,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added support for device selftest. Device selftest includes checking the status of firmware. Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_ops.c | 57 ++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c index 2d7d760536..2fa0522faf 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.c +++ b/drivers/ml/cnxk/cn10k_ml_ops.c @@ -686,6 +686,62 @@ cn10k_ml_dev_dump(struct rte_ml_dev *dev, FILE *fp) return 0; } +static int +cn10k_ml_dev_selftest(struct rte_ml_dev *dev) +{ + const struct plt_memzone *mz; + struct cn10k_ml_dev *mldev; + struct cn10k_ml_req *req; + uint64_t timeout_cycle; + bool timeout; + int ret; + + mldev = dev->data->dev_private; + mz = plt_memzone_reserve_aligned("dev_selftest", sizeof(struct cn10k_ml_req), 0, + ML_CN10K_ALIGN_SIZE); + if (mz == NULL) { + plt_err("Could not allocate reserved memzone"); + return -ENOMEM; + } + req = mz->addr; + + /* Prepare load completion structure */ + memset(&req->jd, 0, sizeof(struct cn10k_ml_jd)); + req->jd.hdr.jce.w1.u64 = PLT_U64_CAST(&req->status); + req->jd.hdr.job_type = ML_CN10K_JOB_TYPE_FIRMWARE_SELFTEST; + req->jd.hdr.result = roc_ml_addr_ap2mlip(&mldev->roc, &req->result); + req->jd.fw_load.flags = cn10k_ml_fw_flags_get(&mldev->fw); + plt_write64(ML_CN10K_POLL_JOB_START, &req->status); + plt_wmb(); + + /* Enqueue firmware selftest request through scratch registers */ + timeout = true; + timeout_cycle = plt_tsc_cycles() + ML_CN10K_CMD_TIMEOUT * plt_tsc_hz(); + roc_ml_scratch_enqueue(&mldev->roc, &req->jd); + + plt_rmb(); + do { + if (roc_ml_scratch_is_done_bit_set(&mldev->roc) && + (plt_read64(&req->status) == ML_CN10K_POLL_JOB_FINISH)) { + timeout = false; + break; + } + } while (plt_tsc_cycles() < timeout_cycle); + + /* Check firmware selftest status, clean-up and exit */ + ret = 0; + if (timeout) { + ret = -ETIME; + } else { + if (req->result.error_code != 0) + ret = -1; + } + + plt_memzone_free(mz); + + return ret; +} + int cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params, uint16_t *model_id) { @@ -1328,6 +1384,7 @@ struct rte_ml_dev_ops cn10k_ml_ops = { .dev_start = cn10k_ml_dev_start, .dev_stop = cn10k_ml_dev_stop, .dev_dump = cn10k_ml_dev_dump, + .dev_selftest = cn10k_ml_dev_selftest, /* Queue-pair handling ops */ .dev_queue_pair_setup = cn10k_ml_dev_queue_pair_setup, -- 2.17.1