From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ED88A41C30; Tue, 7 Feb 2023 17:10:58 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6841542FBA; Tue, 7 Feb 2023 17:07:58 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 2124442D4A for ; Tue, 7 Feb 2023 17:07:33 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 317EgVTw017206 for ; Tue, 7 Feb 2023 08:07:33 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=chKjMBg3yM5P1HINXXujah3hK3XVMn61vvJ47XuTeNM=; b=CHsC8aW6VHibwJa9EyGpnIBNa5W7uq30N3o66m/zLBUpTJpCkgnWQ526fAiyQYWjFncg bens4GdsHjbA6t6XI3tD3eTJ+CAqxqGzzkoMDJecwv7g2ta3yG/wfORs+H9huknSSqgK ppe18SeX03tAlMXFDC1hCOPr1iacSPi/EWHpCygrQrFzYKbWwaE5p64mntaehqc9SYpt ZG0LokC8u9E56OD9UjnnlAOapLw4zKyG0iH0vqpFVeGIZ3pJhhIuUzf+9+K8eS/ii7qW L4/ApKKX3Io9tKJgh7EkFyge13u5FNuRapt1KMjLZJguvbQy+1PB/fjvHR7mFRiQDynN 8w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3nkdyrssx7-17 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 07 Feb 2023 08:07:33 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 7 Feb 2023 08:07:29 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Tue, 7 Feb 2023 08:07:29 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id AB7CB3F7089; Tue, 7 Feb 2023 08:07:29 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , , , Subject: [PATCH v5 28/39] ml/cnxk: add internal function for sync mode run Date: Tue, 7 Feb 2023 08:07:08 -0800 Message-ID: <20230207160719.1307-29-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230207160719.1307-1-syalavarthi@marvell.com> References: <20221208200220.20267-1-syalavarthi@marvell.com> <20230207160719.1307-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: msOwhs5M3AW4vYHvaKjv0mwya22A_Kgt X-Proofpoint-GUID: msOwhs5M3AW4vYHvaKjv0mwya22A_Kgt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-07_07,2023-02-06_03,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added internal function to execute ML inference requests in synchronous mode. Sync mode inference execution is used to launch inference requests without using a queue-pair. Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_ops.c | 53 ++++++++++++++++++++++++++++++++++ drivers/ml/cnxk/cn10k_ml_ops.h | 1 + 2 files changed, 54 insertions(+) diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c index 51f1c92a8d..87778c37bb 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.c +++ b/drivers/ml/cnxk/cn10k_ml_ops.c @@ -1533,6 +1533,59 @@ cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op return count; } +__rte_hot int +cn10k_ml_inference_sync(struct rte_ml_dev *dev, struct rte_ml_op *op) +{ + struct cn10k_ml_model *model; + struct cn10k_ml_dev *mldev; + struct cn10k_ml_req *req; + bool timeout; + int ret = 0; + + mldev = dev->data->dev_private; + model = dev->data->models[op->model_id]; + req = model->req; + + cn10k_ml_prep_fp_job_descriptor(dev, req, op); + + memset(&req->result, 0, sizeof(struct cn10k_ml_result)); + req->result.user_ptr = op->user_ptr; + + plt_write64(ML_CN10K_POLL_JOB_START, &req->status); + req->jcmd.w1.s.jobptr = PLT_U64_CAST(&req->jd); + + timeout = true; + req->timeout = plt_tsc_cycles() + ML_CN10K_CMD_TIMEOUT * plt_tsc_hz(); + do { + if (roc_ml_jcmdq_enqueue_lf(&mldev->roc, &req->jcmd)) { + req->op = op; + timeout = false; + break; + } + } while (plt_tsc_cycles() < req->timeout); + + if (timeout) { + ret = -EBUSY; + goto error_enqueue; + } + + timeout = true; + do { + if (plt_read64(&req->status) == ML_CN10K_POLL_JOB_FINISH) { + timeout = false; + break; + } + } while (plt_tsc_cycles() < req->timeout); + + if (timeout) + ret = -ETIME; + else + cn10k_ml_result_update(dev, -1, &req->result, req->op); + +error_enqueue: + return ret; +} + struct rte_ml_dev_ops cn10k_ml_ops = { /* Device control ops */ .dev_info_get = cn10k_ml_dev_info_get, diff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h index f6aab4a609..7c35bf7539 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.h +++ b/drivers/ml/cnxk/cn10k_ml_ops.h @@ -75,5 +75,6 @@ __rte_hot uint16_t cn10k_ml_enqueue_burst(struct rte_ml_dev *dev, uint16_t qp_id struct rte_ml_op **ops, uint16_t nb_ops); __rte_hot uint16_t cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op **ops, uint16_t nb_ops); +__rte_hot int cn10k_ml_inference_sync(struct rte_ml_dev *dev, struct rte_ml_op *op); #endif /* _CN10K_ML_OPS_H_ */ -- 2.17.1