From: Chaoyong He <chaoyong.he@corigine.com>
To: dev@dpdk.org
Cc: oss-drivers@corigine.com, niklas.soderlund@corigine.com,
Peng Zhang <peng.zhang@corigine.com>,
jin.liu@corigine.com, stable@dpdk.org,
Chaoyong He <chaoyong.he@corigine.com>
Subject: [PATCH] net/nfp: support 48-bit DMA address for firmware with NFDk
Date: Wed, 8 Feb 2023 17:15:44 +0800 [thread overview]
Message-ID: <20230208091544.22122-1-chaoyong.he@corigine.com> (raw)
From: Peng Zhang <peng.zhang@corigine.com>
48-bit DMA address is supported in the firmware with NFDk, so enable
this feature in PMD now. But the firmware with NFD3 still just
support 40-bit DMA address.
RX free list descriptor, used by both NFD3 and NFDk, is also modified
to support 48-bit DMA address. That's OK because the top bits is always
set to 0 when assigned with 40-bit DMA address.
Fixes: c73dced48c8c ("net/nfp: add NFDk Tx")
Cc: jin.liu@corigine.com
Cc: stable@dpdk.org
Signed-off-by: Peng Zhang <peng.zhang@corigine.com>
Reviewed-by: Chaoyong He <chaoyong.he@corigine.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund@corigine.com>
---
drivers/net/nfp/flower/nfp_flower.c | 12 ++++--------
drivers/net/nfp/flower/nfp_flower_ctrl.c | 2 +-
drivers/net/nfp/nfp_common.c | 18 ++++++++++++++++++
drivers/net/nfp/nfp_common.h | 1 +
drivers/net/nfp/nfp_ethdev.c | 11 +++--------
drivers/net/nfp/nfp_ethdev_vf.c | 11 +++--------
drivers/net/nfp/nfp_rxtx.c | 4 ++--
drivers/net/nfp/nfp_rxtx.h | 4 ++--
8 files changed, 34 insertions(+), 29 deletions(-)
diff --git a/drivers/net/nfp/flower/nfp_flower.c b/drivers/net/nfp/flower/nfp_flower.c
index 7b46dc0f6a..7302d39af5 100644
--- a/drivers/net/nfp/flower/nfp_flower.c
+++ b/drivers/net/nfp/flower/nfp_flower.c
@@ -452,7 +452,7 @@ nfp_flower_pf_recv_pkts(void *rx_queue,
rxds->vals[1] = 0;
dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
rxds->fld.dd = 0;
- rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
+ rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xffff;
rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
nb_hold++;
@@ -632,13 +632,6 @@ nfp_flower_init_vnic_common(struct nfp_net_hw *hw, const char *vnic_type)
pf_dev = hw->pf_dev;
pci_dev = hw->pf_dev->pci_dev;
- /* NFP can not handle DMA addresses requiring more than 40 bits */
- if (rte_mem_check_dma_mask(40)) {
- PMD_INIT_LOG(ERR, "Device %s can not be used: restricted dma mask to 40 bits!\n",
- pci_dev->device.name);
- return -ENODEV;
- };
-
hw->device_id = pci_dev->id.device_id;
hw->vendor_id = pci_dev->id.vendor_id;
hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
@@ -667,6 +660,9 @@ nfp_flower_init_vnic_common(struct nfp_net_hw *hw, const char *vnic_type)
hw->mtu = hw->max_mtu;
hw->flbufsz = DEFAULT_FLBUF_SIZE;
+ if (nfp_net_check_dma_mask(hw, pci_dev->name) != 0)
+ return -ENODEV;
+
/* read the Rx offset configured from firmware */
if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
hw->rx_offset = NFP_NET_RX_OFFSET;
diff --git a/drivers/net/nfp/flower/nfp_flower_ctrl.c b/drivers/net/nfp/flower/nfp_flower_ctrl.c
index 03a2e2e622..b134a74bd8 100644
--- a/drivers/net/nfp/flower/nfp_flower_ctrl.c
+++ b/drivers/net/nfp/flower/nfp_flower_ctrl.c
@@ -122,7 +122,7 @@ nfp_flower_ctrl_vnic_recv(void *rx_queue,
rxds->vals[1] = 0;
dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
rxds->fld.dd = 0;
- rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
+ rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xffff;
rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
nb_hold++;
diff --git a/drivers/net/nfp/nfp_common.c b/drivers/net/nfp/nfp_common.c
index 4f21d9978d..4b36861b21 100644
--- a/drivers/net/nfp/nfp_common.c
+++ b/drivers/net/nfp/nfp_common.c
@@ -1563,6 +1563,24 @@ nfp_net_set_vxlan_port(struct nfp_net_hw *hw,
return ret;
}
+/*
+ * The firmware with NFD3 can not handle DMA address requiring more
+ * than 40 bits
+ */
+int
+nfp_net_check_dma_mask(struct nfp_net_hw *hw, char *name)
+{
+ if (NFD_CFG_CLASS_VER_of(hw->ver) == NFP_NET_CFG_VERSION_DP_NFD3 &&
+ rte_mem_check_dma_mask(40) != 0) {
+ PMD_DRV_LOG(ERR,
+ "The device %s can't be used: restricted dma mask to 40 bits!",
+ name);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
RTE_LOG_REGISTER_SUFFIX(nfp_logtype_init, init, NOTICE);
RTE_LOG_REGISTER_SUFFIX(nfp_logtype_driver, driver, NOTICE);
RTE_LOG_REGISTER_SUFFIX(nfp_logtype_cpp, cpp, NOTICE);
diff --git a/drivers/net/nfp/nfp_common.h b/drivers/net/nfp/nfp_common.h
index 56b7edc951..980f3cad89 100644
--- a/drivers/net/nfp/nfp_common.h
+++ b/drivers/net/nfp/nfp_common.h
@@ -454,6 +454,7 @@ int nfp_net_rx_desc_limits(struct nfp_net_hw *hw,
int nfp_net_tx_desc_limits(struct nfp_net_hw *hw,
uint16_t *min_tx_desc,
uint16_t *max_tx_desc);
+int nfp_net_check_dma_mask(struct nfp_net_hw *hw, char *name);
#define NFP_NET_DEV_PRIVATE_TO_HW(adapter)\
(&((struct nfp_net_adapter *)adapter)->hw)
diff --git a/drivers/net/nfp/nfp_ethdev.c b/drivers/net/nfp/nfp_ethdev.c
index 31201c0197..8ac2a4b5cd 100644
--- a/drivers/net/nfp/nfp_ethdev.c
+++ b/drivers/net/nfp/nfp_ethdev.c
@@ -517,14 +517,6 @@ nfp_net_init(struct rte_eth_dev *eth_dev)
/* Use backpointer to the CoreNIC app struct */
app_fw_nic = NFP_PRIV_TO_APP_FW_NIC(pf_dev->app_fw_priv);
- /* NFP can not handle DMA addresses requiring more than 40 bits */
- if (rte_mem_check_dma_mask(40)) {
- RTE_LOG(ERR, PMD,
- "device %s can not be used: restricted dma mask to 40 bits!\n",
- pci_dev->device.name);
- return -ENODEV;
- }
-
port = ((struct nfp_net_hw *)eth_dev->data->dev_private)->idx;
if (port < 0 || port > 7) {
PMD_DRV_LOG(ERR, "Port value is wrong");
@@ -572,6 +564,9 @@ nfp_net_init(struct rte_eth_dev *eth_dev)
hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
+ if (nfp_net_check_dma_mask(hw, pci_dev->name) != 0)
+ return -ENODEV;
+
if (nfp_net_ethdev_ops_mount(hw, eth_dev))
return -EINVAL;
diff --git a/drivers/net/nfp/nfp_ethdev_vf.c b/drivers/net/nfp/nfp_ethdev_vf.c
index 4eea197f85..e60e9f0f15 100644
--- a/drivers/net/nfp/nfp_ethdev_vf.c
+++ b/drivers/net/nfp/nfp_ethdev_vf.c
@@ -291,14 +291,6 @@ nfp_netvf_init(struct rte_eth_dev *eth_dev)
pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- /* NFP can not handle DMA addresses requiring more than 40 bits */
- if (rte_mem_check_dma_mask(40)) {
- RTE_LOG(ERR, PMD,
- "device %s can not be used: restricted dma mask to 40 bits!\n",
- pci_dev->device.name);
- return -ENODEV;
- }
-
hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
@@ -312,6 +304,9 @@ nfp_netvf_init(struct rte_eth_dev *eth_dev)
hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
+ if (nfp_net_check_dma_mask(hw, pci_dev->name) != 0)
+ return -ENODEV;
+
if (nfp_netvf_ethdev_ops_mount(hw, eth_dev))
return -EINVAL;
diff --git a/drivers/net/nfp/nfp_rxtx.c b/drivers/net/nfp/nfp_rxtx.c
index 4a7574fd65..5ca3aef7e1 100644
--- a/drivers/net/nfp/nfp_rxtx.c
+++ b/drivers/net/nfp/nfp_rxtx.c
@@ -48,7 +48,7 @@ nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
rxd = &rxq->rxds[i];
rxd->fld.dd = 0;
- rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
+ rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xffff;
rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
rxe[i].mbuf = mbuf;
PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
@@ -454,7 +454,7 @@ nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
rxds->vals[1] = 0;
dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
rxds->fld.dd = 0;
- rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
+ rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xffff;
rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
nb_hold++;
diff --git a/drivers/net/nfp/nfp_rxtx.h b/drivers/net/nfp/nfp_rxtx.h
index 8a29adbd73..765717e8dc 100644
--- a/drivers/net/nfp/nfp_rxtx.h
+++ b/drivers/net/nfp/nfp_rxtx.h
@@ -287,8 +287,8 @@ struct nfp_net_rx_desc {
union {
/* Freelist descriptor */
struct {
- uint8_t dma_addr_hi;
- __le16 spare;
+ __le16 dma_addr_hi;
+ uint8_t spare;
uint8_t dd;
__le32 dma_addr_lo;
--
2.29.3
next reply other threads:[~2023-02-08 9:16 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-08 9:15 Chaoyong He [this message]
2023-02-15 13:42 ` Ferruh Yigit
2023-02-15 17:47 ` Niklas Söderlund
2023-02-15 18:28 ` Ferruh Yigit
2023-02-16 10:28 ` Kevin Traynor
2023-02-16 10:37 ` Niklas Söderlund
2023-02-16 10:41 ` Chaoyong He
2023-02-16 10:55 ` Niklas Soderlund
2023-02-16 10:59 ` Ferruh Yigit
2023-02-16 11:11 ` Nole Zhang
2023-02-16 11:17 ` Ferruh Yigit
2023-02-20 9:02 ` [PATCH v2] net/nfp: fix 48-bit DMA address support for NFDk Chaoyong He
2023-02-20 14:02 ` Ferruh Yigit
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