From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7FA1B41C88; Mon, 13 Feb 2023 12:38:29 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 661B842D2C; Mon, 13 Feb 2023 12:38:20 +0100 (CET) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2079.outbound.protection.outlook.com [40.107.94.79]) by mails.dpdk.org (Postfix) with ESMTP id 6205442D0D for ; Mon, 13 Feb 2023 12:38:19 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZXPYMi85m8xI4bSpI6+a5l5Sb/cndxUyUAbzY4Q4uDT2ASwtvbZRc5O3V4TsPj4Ju2jK48LmAOXMlHY6JegqtFZL47hgpFQc457D3VaMMlZqn37io2d/ZQZgReCOrTXWTFJdBsB4OPv2Lgi10kwBzpnEGHTIyj3n+KYembWNIVSlzDvRxgBfcGYn/hKBkzl51Ep7NU5bWYSpHQpD9RO2rFkUf/0g9V5c5hKkVbHyP8RuKo0tgp4SF7m7UVw9FrL0b8imSNA+PcmB8qtRPXgeF2FQ6btBlpJGucTL9JRZHdOQb4TgOKPCHXh5NKQN65mh9Qb4VWuv+loKw+pl63yNwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=BhILZ50TmdvWV7AGZukbPsrJmQDTgXNxgnBRA4QMgPc=; b=JyvF2Q48UkPUyXfyPV/lFfeewV75EehMvHk/AJUFZg7L/oRgSU5/1wvHBT91lU3X3hNk8RNzTdutAALBP6jf/JBUtijs0VQkINGR18HvvZzQNY18iN7HfdGnXbChIbPiH03unecDrNg4mKg95oYYWad9+vMCh5B3j40U14Hr2w4pFPK+LDiBzR4OfF6uU086Vm1/vbapcT5cm3KXA97UqRDerIgYVJVGasvlcE/rRb5tIzkUrA1rVGbbha6Tpp8g9kSSrTiZXw2/7w+FbSLKfilUo2/w52/ZFaOKSa8IY+I7JIIFiEvReEJw1wZLmFtqoviKuqTpAEOtObEzTeAh2w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BhILZ50TmdvWV7AGZukbPsrJmQDTgXNxgnBRA4QMgPc=; b=WUnqe0xoKh6Rn7m/nBYNFKSOfWQnEpk7S3vV1HENrRfZ6wV1b2hwV5H5kQQ3M2FNcwdPpfamQpafj0OyUKuoUPDtJB3OPqa4VOqJTubDBQ1aIFkM6YBWhoURV2MaU+yd/hEsZJHxQr33X1NPzY+jxH8WHNBxrWtX062qyq6cTQtmR4Hm4E1ArjgN+pdwd8p4UU0oW3MvRfrE+/Wz3BRYsiIa8096MPxOzzlUq+S56QnOlZbg7GJ+Aha/Wl+z6YSoKH6RguU/0va26xiaSDeI9jJVFYQPLJHJTvcmUp3dLGtt1vqVuDfaV8+HsaAypib6JObQBLFVt6+Y1RXKlk+/og== Received: from DM6PR02CA0085.namprd02.prod.outlook.com (2603:10b6:5:1f4::26) by MN2PR12MB4533.namprd12.prod.outlook.com (2603:10b6:208:266::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.24; Mon, 13 Feb 2023 11:38:16 +0000 Received: from DM6NAM11FT076.eop-nam11.prod.protection.outlook.com (2603:10b6:5:1f4:cafe::93) by DM6PR02CA0085.outlook.office365.com (2603:10b6:5:1f4::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.24 via Frontend Transport; Mon, 13 Feb 2023 11:38:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT076.mail.protection.outlook.com (10.13.173.204) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.24 via Frontend Transport; Mon, 13 Feb 2023 11:38:16 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 13 Feb 2023 03:38:06 -0800 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 13 Feb 2023 03:38:03 -0800 From: Rongwei Liu To: , , , , CC: , Gregory Etelson , Alex Vesker Subject: [PATCH v2 2/5] net/mlx5/hws: Definer, add mlx5dr context to definer_conv_data Date: Mon, 13 Feb 2023 13:37:44 +0200 Message-ID: <20230213113747.3677487-3-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230213113747.3677487-1-rongweil@nvidia.com> References: <20230202101128.2446928-2-rongweil@nvidia.com> <20230213113747.3677487-1-rongweil@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT076:EE_|MN2PR12MB4533:EE_ X-MS-Office365-Filtering-Correlation-Id: 06b77e26-914e-4038-2575-08db0db6cc14 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 88KyhhRMxHBaXRz0hxTaai1WyCk+h6pI1asJB1xqZJl+CAVGIJseN+NKTZfF2B189Ie27x/ih+vmD/BNPxJkf+X+7dEi+v7ICd4sUn8StZJWJQGyPg8q3kyLL525fTLiuEXriENlrJutE1xzLMpvn3JUsYzPRQ+gkl/GoJeULYfUJMg5euD2hYRPWXGAiCKaBZnh4F8A+/K2kch6TsJxEcsP9OdHqmEJob5y2jNCGOimu9YIUjl/cK0YobfxdgyeegWM8gQb0GEhVll3DQBbwr2AjOR8YY1lXLLlxR/5lJNZQCPTWtfVeyJ5ZHSHJLmANz/iaNlT84GN7KOno3ZS6sy7dILjxfXbJh2AytDFRTSF5TLQSozXmc4nhgkC0xvIgWQPZz4uPKsQ+dHH8MyhcUMqtenWpDuTTfTcwJkNuYkiPw0ns8TVHFUXDyIT6RwfU2iFIx5RKROVwdluOsfH4kHrBujnOqkQv88XW7sdUD126iHm2I92s9FPitlreO04ZI2oGHGde88QFLv2bASeq8G2JfY2aDcHsadYn5L1HcT1QP7lw38qjeEhiFoPQgsXzXTQBEIi5tYVjmOODCejzqe5yBSvPOfHDD30p3kdSiprw85YUes9PzXchGOjLEBDIkgyBdE88OuRiyO3ABGc1j/Je0GRilCJz2sNjKyO2m88RmeViPo3nQZf14FPlZtSFwjkSP+JlsRngsfIZ/3k/rqmV4QWqf282/be8hiPNPo+eQrV4rTZsaKc6jZckvv1 X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(39860400002)(396003)(346002)(376002)(136003)(451199018)(40470700004)(46966006)(36840700001)(36756003)(40460700003)(41300700001)(54906003)(316002)(110136005)(4326008)(356005)(70206006)(8676002)(70586007)(40480700001)(55016003)(36860700001)(86362001)(82310400005)(82740400003)(7636003)(7696005)(6666004)(107886003)(1076003)(6286002)(26005)(186003)(16526019)(2906002)(5660300002)(2616005)(8936002)(478600001)(47076005)(426003)(336012)(83380400001)(42413004)(32563001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2023 11:38:16.0732 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 06b77e26-914e-4038-2575-08db0db6cc14 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT076.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4533 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Gregory Etelson New mlx5dr_context member replaces mlx5dr_cmd_query_caps. Capabilities structure is a member of mlx5dr_context. Signed-off-by: Gregory Etelson Signed-off-by: Rongwei Liu Reviewed-by: Alex Vesker Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/hws/mlx5dr_definer.c | 41 ++++++++++++++------------- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 4849158407..e7b42ee912 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -100,7 +100,7 @@ struct mlx5dr_definer_sel_ctrl { }; struct mlx5dr_definer_conv_data { - struct mlx5dr_cmd_query_caps *caps; + struct mlx5dr_context *ctx; struct mlx5dr_definer_fc *fc; uint8_t relaxed; uint8_t tunnel; @@ -888,6 +888,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, int item_idx) { + struct mlx5dr_cmd_query_caps *caps = cd->ctx->caps; const struct rte_flow_item_gtp *m = item->mask; struct mlx5dr_definer_fc *fc; @@ -909,7 +910,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, } if (m->hdr.teid) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_TEID_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_TEID_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -917,11 +918,11 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, fc->item_idx = item_idx; fc->tag_set = &mlx5dr_definer_gtp_teid_set; fc->bit_mask = __mlx5_mask(header_gtp, teid); - fc->byte_off = cd->caps->format_select_gtpu_dw_1 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_1 * DW_SIZE; } if (m->hdr.gtp_hdr_info) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -930,12 +931,12 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_ext_flag_set; fc->bit_mask = __mlx5_mask(header_gtp, ext_hdr_flag); fc->bit_off = __mlx5_dw_bit_off(header_gtp, ext_hdr_flag); - fc->byte_off = cd->caps->format_select_gtpu_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_0 * DW_SIZE; } if (m->hdr.msg_type) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -944,7 +945,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_msg_type_set; fc->bit_mask = __mlx5_mask(header_gtp, msg_type); fc->bit_off = __mlx5_dw_bit_off(header_gtp, msg_type); - fc->byte_off = cd->caps->format_select_gtpu_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_0 * DW_SIZE; } return 0; @@ -955,12 +956,13 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, int item_idx) { + struct mlx5dr_cmd_query_caps *caps = cd->ctx->caps; const struct rte_flow_item_gtp_psc *m = item->mask; struct mlx5dr_definer_fc *fc; /* Overwrite GTP extension flag to be 1 */ if (!cd->relaxed) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -969,12 +971,12 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_ones_set; fc->bit_mask = __mlx5_mask(header_gtp, ext_hdr_flag); fc->bit_off = __mlx5_dw_bit_off(header_gtp, ext_hdr_flag); - fc->byte_off = cd->caps->format_select_gtpu_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_0 * DW_SIZE; } /* Overwrite next extension header type */ if (!cd->relaxed) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_2_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_2_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -984,14 +986,14 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_mask_set = &mlx5dr_definer_ones_set; fc->bit_mask = __mlx5_mask(header_opt_gtp, next_ext_hdr_type); fc->bit_off = __mlx5_dw_bit_off(header_opt_gtp, next_ext_hdr_type); - fc->byte_off = cd->caps->format_select_gtpu_dw_2 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_2 * DW_SIZE; } if (!m) return 0; if (m->hdr.type) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -1000,11 +1002,11 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_ext_hdr_pdu_set; fc->bit_mask = __mlx5_mask(header_gtp_psc, pdu_type); fc->bit_off = __mlx5_dw_bit_off(header_gtp_psc, pdu_type); - fc->byte_off = cd->caps->format_select_gtpu_ext_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_ext_dw_0 * DW_SIZE; } if (m->hdr.qfi) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -1013,7 +1015,7 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_ext_hdr_qfi_set; fc->bit_mask = __mlx5_mask(header_gtp_psc, qfi); fc->bit_off = __mlx5_dw_bit_off(header_gtp_psc, qfi); - fc->byte_off = cd->caps->format_select_gtpu_ext_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_ext_dw_0 * DW_SIZE; } return 0; @@ -1024,18 +1026,19 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, int item_idx) { + struct mlx5dr_cmd_query_caps *caps = cd->ctx->caps; const struct rte_flow_item_ethdev *m = item->mask; struct mlx5dr_definer_fc *fc; uint8_t bit_offset = 0; if (m->port_id) { - if (!cd->caps->wire_regc_mask) { + if (!caps->wire_regc_mask) { DR_LOG(ERR, "Port ID item not supported, missing wire REGC mask"); rte_errno = ENOTSUP; return rte_errno; } - while (!(cd->caps->wire_regc_mask & (1 << bit_offset))) + while (!(caps->wire_regc_mask & (1 << bit_offset))) bit_offset++; fc = &cd->fc[MLX5DR_DEFINER_FNAME_VPORT_REG_C_0]; @@ -1044,7 +1047,7 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd, fc->tag_mask_set = &mlx5dr_definer_ones_set; DR_CALC_SET_HDR(fc, registers, register_c_0); fc->bit_off = bit_offset; - fc->bit_mask = cd->caps->wire_regc_mask >> bit_offset; + fc->bit_mask = caps->wire_regc_mask >> bit_offset; } else { DR_LOG(ERR, "Pord ID item mask must specify ID mask"); rte_errno = EINVAL; @@ -1657,7 +1660,7 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, int i, ret; cd.fc = fc; - cd.caps = ctx->caps; + cd.ctx = ctx; cd.relaxed = mt->flags & MLX5DR_MATCH_TEMPLATE_FLAG_RELAXED_MATCH; /* Collect all RTE fields to the field array and set header layout */ -- 2.27.0