From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D995A41CB1; Thu, 16 Feb 2023 12:09:44 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2FBD842D38; Thu, 16 Feb 2023 12:09:37 +0100 (CET) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id ABBF442D13; Thu, 16 Feb 2023 12:09:34 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676545775; x=1708081775; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LDWexLDGdfmEhEoxP/d8EPH75KfCbNNZAPyABqtfk9Y=; b=Iv7b8hh2w4wXiaLxQC296HHAwU32rPqzeDgMV8cPeIOIZPm24X9mr7N5 +mK8I5vWWWkPIU1WkKBe4EuChUEiIeenVDZhOu/UaZ1qJmwqBbSY5NXHE FnDxHKEbDeH7iXsM6g4k9R0x5QaPW8/uNWPojnSU2aLASghZ21tzYQ6CN 6YlZ2xqcJe3GHji6F7//rhXg09TP/TQEAgCnDCnT3mgmVbXFkTynoYJ2i XQ78n7k+QjtCFkLutsc9kbG+S2TxwFB0T4tFLsMkvqzaxEXfSY8tWyYOe Wc7DTjSEoLroKJhj1oTQSI9jarDV71917nf484MlhmLd3g/vlvM+EHRIz g==; X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="315368156" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="315368156" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2023 03:09:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10622"; a="702522824" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="702522824" Received: from silpixa00401385.ir.intel.com ([10.237.214.22]) by orsmga001.jf.intel.com with ESMTP; 16 Feb 2023 03:09:32 -0800 From: Bruce Richardson To: dev@dpdk.org Cc: fengchengwen@huawei.com, Bruce Richardson , conor.walsh@intel.com, stable@dpdk.org, Kevin Laatz Subject: [PATCH v3 2/6] dma/ioat: fix incorrectly set indexes after restart Date: Thu, 16 Feb 2023 11:09:15 +0000 Message-Id: <20230216110919.373385-3-bruce.richardson@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230216110919.373385-1-bruce.richardson@intel.com> References: <20230116153714.554470-1-bruce.richardson@intel.com> <20230216110919.373385-1-bruce.richardson@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org As part of the process of restarting a dma instance, the IOAT driver will reset the HW addresses and state values. The read and write indexes for SW use need to be similarly reset to keep HW and SW in sync. Fixes: 583f046dd404 ("dma/ioat: add start and stop") Cc: conor.walsh@intel.com Cc: stable@dpdk.org Signed-off-by: Bruce Richardson Reviewed-by: Conor Walsh Acked-by: Kevin Laatz --- drivers/dma/ioat/ioat_dmadev.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/dma/ioat/ioat_dmadev.c b/drivers/dma/ioat/ioat_dmadev.c index aff7bbbfde..072eb17cd9 100644 --- a/drivers/dma/ioat/ioat_dmadev.c +++ b/drivers/dma/ioat/ioat_dmadev.c @@ -146,6 +146,13 @@ ioat_dev_start(struct rte_dma_dev *dev) /* Prime the status register to be set to the last element. */ ioat->status = ioat->ring_addr + ((ioat->qcfg.nb_desc - 1) * DESC_SZ); + /* reset all counters */ + ioat->next_read = 0; + ioat->next_write = 0; + ioat->last_write = 0; + ioat->offset = 0; + ioat->failure = 0; + printf("IOAT.status: %s [0x%"PRIx64"]\n", chansts_readable[ioat->status & IOAT_CHANSTS_STATUS], ioat->status); -- 2.37.2