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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT081.mail.protection.outlook.com (10.13.172.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6134.17 via Frontend Transport; Tue, 21 Feb 2023 07:48:31 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 20 Feb 2023 23:48:24 -0800 Received: from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 20 Feb 2023 23:48:23 -0800 From: Gerry Gribbon To: CC: , Ori Kam Subject: [PATCH] regex/mlx5: utilize all available QPs Date: Tue, 21 Feb 2023 07:47:28 +0000 Message-ID: <20230221074728.1486004-1-ggribbon@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT081:EE_|PH8PR12MB6937:EE_ X-MS-Office365-Filtering-Correlation-Id: a2e6ff94-99d8-4b41-fb82-08db13e006f0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Feb 2023 07:48:31.1709 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a2e6ff94-99d8-4b41-fb82-08db13e006f0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT081.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6937 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix overflow of free QP mask. Regex used 64 QPs and used a bitmask to select a free QP for use. The bitmask in use was only 32 bits so did not allow half of the QPs to be utilised. Upgraded to 64 bit mask and using ffsll now instead of ffs. Fixes: 270032608503 ("regex/mlx5: refactor HW queue objects") Cc: stable@dpdk.org Signed-off-by: Gerry Gribbon --- drivers/regex/mlx5/mlx5_regex.h | 2 +- drivers/regex/mlx5/mlx5_regex_fastpath.c | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h index b8554fd1cf..481f6fc59f 100644 --- a/drivers/regex/mlx5/mlx5_regex.h +++ b/drivers/regex/mlx5/mlx5_regex.h @@ -37,7 +37,7 @@ struct mlx5_regex_qp { struct mlx5_regex_hw_qp *qps; /* Pointer to qp array. */ uint16_t nb_obj; /* Number of qp objects. */ struct mlx5_regex_cq cq; /* CQ struct. */ - uint32_t free_qps; + uint64_t free_qps; struct mlx5_regex_job *jobs; struct ibv_mr *metadata; struct ibv_mr *outputs; diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c index 143c7d7cdf..6c87afa923 100644 --- a/drivers/regex/mlx5/mlx5_regex_fastpath.c +++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c @@ -417,7 +417,7 @@ mlx5_regexdev_enqueue_gga(struct rte_regexdev *dev, uint16_t qp_id, return 0; #endif - while ((hw_qpid = ffs(queue->free_qps))) { + while ((hw_qpid = ffsll(queue->free_qps))) { hw_qpid--; /* ffs returns 1 for bit 0 */ qp_obj = &queue->qps[hw_qpid]; nb_desc = get_free(qp_obj, priv->has_umr); @@ -426,7 +426,7 @@ mlx5_regexdev_enqueue_gga(struct rte_regexdev *dev, uint16_t qp_id, if (nb_desc > nb_left) nb_desc = nb_left; else - queue->free_qps &= ~(1 << hw_qpid); + queue->free_qps &= ~(1ULL << hw_qpid); prep_regex_umr_wqe_set(priv, queue, qp_obj, ops, nb_desc); send_doorbell(priv, qp_obj); @@ -456,7 +456,7 @@ mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, return 0; #endif - while ((hw_qpid = ffs(queue->free_qps))) { + while ((hw_qpid = ffsll(queue->free_qps))) { hw_qpid--; /* ffs returns 1 for bit 0 */ qp_obj = &queue->qps[hw_qpid]; while (get_free(qp_obj, priv->has_umr)) { @@ -470,7 +470,7 @@ mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, goto out; } } - queue->free_qps &= ~(1 << hw_qpid); + queue->free_qps &= ~(1ULL << hw_qpid); send_doorbell(priv, qp_obj); } @@ -603,7 +603,7 @@ mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, cq->ci = (cq->ci + 1) & 0xffffff; rte_wmb(); cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->ci); - queue->free_qps |= (1 << hw_qpid); + queue->free_qps |= (1ULL << hw_qpid); } out: @@ -642,7 +642,7 @@ setup_qps(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *queue) (uintptr_t)job->output); wqe += 64; } - queue->free_qps |= 1 << hw_qpid; + queue->free_qps |= 1ULL << hw_qpid; } } -- 2.25.1