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Wed, 22 Feb 2023 23:47:41 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam Subject: [PATCH v3 2/2] net/mlx5: add MPLS tunnel support for HWS Date: Thu, 23 Feb 2023 09:47:34 +0200 Message-ID: <20230223074734.3315320-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230223074734.3315320-1-michaelba@nvidia.com> References: <20230222212310.3295762-1-michaelba@nvidia.com> <20230223074734.3315320-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT099:EE_|SN7PR12MB7912:EE_ X-MS-Office365-Filtering-Correlation-Id: 6764c1c4-7f2e-4d55-51ff-08db157246f7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1rx9ZFENzdZtW04afyjh/0J+PuzNWI3aJn2a7nKyMH1z1MUZ40+NDvBLEQH0WUvddEsiCaWbv28AGt3fVN/slkMNtr5JscqCIxDkJ9A++E6B9HEIv6rXB5omzN3dsBFwu6f++h/WtBCmaJKe7biVrVII3T40bcnL6IiPp7cGW5nP358sTOjUgdmncuyQBFd9Z8avt+LaEiAanjlJmBHkRQbQB41ox0401IyNzmE6aymBkV0NhJKOV9seiO9lVoIyTQXcbnJo8tqy9n0seVnXUt7xicjPVkpIpfmAUIdUOIZF5fzTS5AG2SJ9TXYFCOcojyLGEUyMJ/5vKeVvT98Ve2QtscQLApKtSyWLzrN9YYB/PvrP0JM5tAR6WZNXlVI1d92OUTHNQpISOW9uY+/nusmwrc8HLNfvt9jS0nXpo/2yathPBBgArYakAlLbi2MH3PSqLXjbEi4gGiIwWkY+GSMJS+Y5Ie4bDk9fzmd3+t8SI9Srk/egm57j8LJ3QYfVxNubw9RSlyR+ePXQ4X/NLHkFHDFkJcIHD8LTappVXqHjQNSKCIdDt3q809KJUwV6Rdf32w+PbX9ZTnhbq8pzCtOjirlJGOG/+hAvnvXXQX1NRU4TU/UlUUr0PE71L+KEb+h71MPiY3l6Fk7GmHgtfPl1TjEOEAneYcEh9v6v0+EiszUDDfqTuQH24zaTj32RizXRa6uMfRkZ0VpNQSOV7/0343fz8lz0cJhv9ISbZn8= X-Forefront-Antispam-Report: CIP:216.228.117.160; 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Signed-off-by: Michael Baum Acked-by: Ori Kam --- doc/guides/nics/mlx5.rst | 4 ++++ doc/guides/rel_notes/release_23_03.rst | 1 + drivers/net/mlx5/mlx5_flow_hw.c | 1 + 3 files changed, 6 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index f9b3d43378..4142933b0d 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -245,6 +245,10 @@ Limitations - L3 VXLAN and VXLAN-GPE tunnels cannot be supported together with MPLSoGRE and MPLSoUDP. +- MPLSoGRE is not supported in HW steering (``dv_flow_en`` = 2). + +- MPLSoUDP with multiple MPLS headers is only supported in HW steering (``dv_flow_en`` = 2). + - Match on Geneve header supports the following fields only: - VNI diff --git a/doc/guides/rel_notes/release_23_03.rst b/doc/guides/rel_notes/release_23_03.rst index 2ca30b3b49..8a3988c033 100644 --- a/doc/guides/rel_notes/release_23_03.rst +++ b/doc/guides/rel_notes/release_23_03.rst @@ -114,6 +114,7 @@ New Features * **Updated NVIDIA mlx5 driver.** * Added support for matching on ICMPv6 ID and sequence fields. + * Added support for MPLSoUDP in hardware steering. * **Updated Wangxun ngbe driver.** diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index a9c7045a3e..80d4beeecd 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -4733,6 +4733,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, case RTE_FLOW_ITEM_TYPE_GTP: case RTE_FLOW_ITEM_TYPE_GTP_PSC: case RTE_FLOW_ITEM_TYPE_VXLAN: + case RTE_FLOW_ITEM_TYPE_MPLS: case MLX5_RTE_FLOW_ITEM_TYPE_SQ: case RTE_FLOW_ITEM_TYPE_GRE: case RTE_FLOW_ITEM_TYPE_GRE_KEY: -- 2.25.1