From: Alexander Kozyrev <akozyrev@nvidia.com>
To: <dev@dpdk.org>
Cc: <rasland@nvidia.com>, <viacheslavo@nvidia.com>, <matan@nvidia.com>
Subject: [PATCH 1/5] common/mlx5: detect enhanced CQE compression capability
Date: Tue, 28 Feb 2023 18:43:06 +0200 [thread overview]
Message-ID: <20230228164310.807594-2-akozyrev@nvidia.com> (raw)
In-Reply-To: <20230228164310.807594-1-akozyrev@nvidia.com>
Enhanced CQE Compression is designed for better latency and SW utilization.
Check the HCA capabilities to see if Enhanced CQE Compression is supported.
Basic or Enhanced CQE Compression can be set as the CQE Compression Layout.
Enhanced CQE Compression can be selected only if it is supported by the FW.
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++
drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++
drivers/common/mlx5/mlx5_prm.h | 30 +++++++++++++++++++++++-----
3 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index bfc6e09eac..8b5582701f 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1001,6 +1001,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
mini_cqe_resp_flow_tag);
attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
mini_cqe_resp_l3_l4_tag);
+ attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr,
+ enhanced_cqe_compression);
attr->umr_indirect_mkey_disabled =
MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
attr->umr_modify_entity_size_disabled =
@@ -2059,6 +2061,7 @@ mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
+ MLX5_SET(cqc, cqctx, cqe_comp_layout, !!attr->cqe_comp_layout);
MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
attr->mini_cqe_res_format_ext);
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 8e68eeaf37..44b627daf2 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -244,6 +244,7 @@ struct mlx5_hca_attr {
uint32_t cqe_compression:1;
uint32_t mini_cqe_resp_flow_tag:1;
uint32_t mini_cqe_resp_l3_l4_tag:1;
+ uint32_t enhanced_cqe_compression:1;
uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */
struct mlx5_hca_qos_attr qos;
struct mlx5_hca_vdpa_attr vdpa;
@@ -468,6 +469,7 @@ struct mlx5_devx_cq_attr {
uint32_t cqe_comp_en:1;
uint32_t mini_cqe_res_format:2;
uint32_t mini_cqe_res_format_ext:2;
+ uint32_t cqe_comp_layout:2;
uint32_t log_cq_size:5;
uint32_t log_page_size:5;
uint32_t uar_page_id;
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 54766c2d65..aa291f19a6 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -1715,10 +1715,28 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 max_geneve_tlv_options[0x8];
u8 reserved_at_568[0x3];
u8 max_geneve_tlv_option_data_len[0x5];
- u8 reserved_at_570[0x49];
+ u8 flex_parser_header_modify[0x1];
+ u8 reserved_at_571[0x2];
+ u8 log_max_guaranteed_connections[0x5];
+ u8 driver_version_before_init_hca[0x1];
+ u8 adv_virtualization[0x1];
+ u8 reserved_at_57a[0x1];
+ u8 log_max_dct_connections[0x5];
+ u8 log_max_atomic_size_qp[0x8];
+ u8 reserved_at_587[0x3];
+ u8 log_max_dci_stream_channels[0x5];
+ u8 reserved_at_58f[0x3];
+ u8 log_max_dci_errored_streams[0x5];
+ u8 log_max_atomic_dize_dc[0x8];
+ u8 max_multi_user_ggroup_size[0x10];
+ u8 enhanced_cqe_compression[0x1];
+ u8 reserved_at_5b0[0x1];
+ u8 crossing_vhca_mkey[0x1];
+ u8 log_max_dek[0x5];
+ u8 reserved_at_5b7[0x1];
u8 mini_cqe_resp_l3_l4_tag[0x1];
u8 mini_cqe_resp_flow_tag[0x1];
- u8 enhanced_cqe_compression[0x1];
+ u8 reserved_at_5ba[0x1];
u8 mini_cqe_resp_stride_index[0x1];
u8 cqe_128_always[0x1];
u8 cqe_compression_128[0x1];
@@ -3042,7 +3060,7 @@ struct mlx5_ifc_cqc_bits {
u8 as_notify[0x1];
u8 initiator_src_dct[0x1];
u8 dbr_umem_valid[0x1];
- u8 reserved_at_7[0x1];
+ u8 ext_element[0x1];
u8 cqe_sz[0x3];
u8 cc[0x1];
u8 reserved_at_c[0x1];
@@ -3052,8 +3070,10 @@ struct mlx5_ifc_cqc_bits {
u8 cqe_comp_en[0x1];
u8 mini_cqe_res_format[0x2];
u8 st[0x4];
- u8 reserved_at_18[0x1];
- u8 cqe_comp_layout[0x7];
+ u8 always_armed_cq[0x1];
+ u8 ext_element_type[0x3];
+ u8 reserved_at_1c[0x2];
+ u8 cqe_comp_layout[0x2];
u8 dbr_umem_id[0x20];
u8 reserved_at_40[0x14];
u8 page_offset[0x6];
--
2.18.2
next prev parent reply other threads:[~2023-02-28 16:43 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-28 16:43 [PATCH 0/5] net/mlx5: enhanced CQE compression layout Alexander Kozyrev
2023-02-28 16:43 ` Alexander Kozyrev [this message]
2023-03-06 12:33 ` [PATCH 1/5] common/mlx5: detect enhanced CQE compression capability Slava Ovsiienko
2023-02-28 16:43 ` [PATCH 2/5] common/mlx5: add CQE validity iteration count Alexander Kozyrev
2023-03-06 12:39 ` Slava Ovsiienko
2023-02-28 16:43 ` [PATCH 3/5] net/mlx5: support enhanced CQE compression in Rx burst Alexander Kozyrev
2023-03-06 13:01 ` Slava Ovsiienko
2023-02-28 16:43 ` [PATCH 4/5] net/mlx5: support enhanced CQE zipping in vector " Alexander Kozyrev
2023-03-06 13:13 ` Slava Ovsiienko
2023-02-28 16:43 ` [PATCH 5/5] net/mlx5: enable enhanced CQE compression Alexander Kozyrev
2023-03-06 13:14 ` Slava Ovsiienko
2023-03-07 9:03 ` [PATCH 0/5] net/mlx5: enhanced CQE compression layout Raslan Darawsheh
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