From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BE40A41DC3; Fri, 3 Mar 2023 09:12:11 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D104142D3B; Fri, 3 Mar 2023 09:11:28 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 2AA85410EC for ; Fri, 3 Mar 2023 09:11:27 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3236qKH8004462 for ; Fri, 3 Mar 2023 00:11:26 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=d4BpF/zqhL1mGI/ErZXODUDNh+F9Oe0cCNJcGWYxFK0=; b=hfRZJoAf0VRDKhARxR5YQkLM7iLWk0DMnR+IPQbxvswfZu4q/JrB79O/hKtsuwh7OxWg JhuZGBdkIKH0XZhPFzDcqNW4KblBC5AgKWtAZSXWh7gss7Svzgbhb13WK1uaVxJjr2Hp r9EuPnA9d5MTa2srGbIqGdqn5ybSbu0T5AvBpMGiPPpmsjQuyjwm0blgmRjaeZCuBh36 JZq6sWxlu8LdT9M/73VTF0Z427ufyjyyhpoERmk+ljrCQq8EzwayybDugj3w/ZFl9GDz 0PuUwU8TvBG0n+Q8sRo8DCf/RO+gRjOaX20WODqtRtvOpGWHIa9YhvoEYoSMvvCjvi3t 8Q== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3p1wr9xbks-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 03 Mar 2023 00:11:26 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 3 Mar 2023 00:11:24 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 3 Mar 2023 00:11:24 -0800 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 7BF0A5B6969; Fri, 3 Mar 2023 00:11:18 -0800 (PST) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Harman Kalra Subject: [PATCH 12/15] common/cnxk: enable one to one SQ QINT mapping Date: Fri, 3 Mar 2023 13:40:10 +0530 Message-ID: <20230303081013.589868-12-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303081013.589868-1-ndabilpuram@marvell.com> References: <20230303081013.589868-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: SCb5lKg2lSSslX2s4M3NC3et1hO63HL- X-Proofpoint-GUID: SCb5lKg2lSSslX2s4M3NC3et1hO63HL- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-03_01,2023-03-02_02,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Harman Kalra Enabling one to one mapping between SQ to 64 QINTs per LF. So in case of SQ interrupt event NIX can deliver associated QINT MSI-X interrupt to software and increment respective QINT count CSR. While for some cn10k chip models keeping the workaround (i.e. all SQs assigned to same QINT index), for errata where NIX may use an incorrect QINT_IDX for SQ interrupts. Signed-off-by: Harman Kalra --- drivers/common/cnxk/roc_errata.h | 8 ++++++++ drivers/common/cnxk/roc_nix_queue.c | 21 +++++++++++---------- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/common/cnxk/roc_errata.h b/drivers/common/cnxk/roc_errata.h index 36e6db467a..356f9ca626 100644 --- a/drivers/common/cnxk/roc_errata.h +++ b/drivers/common/cnxk/roc_errata.h @@ -98,4 +98,12 @@ roc_errata_nix_sdp_send_has_mtu_size_16k(void) roc_model_is_cn96_a0() || roc_model_is_cn96_b0()); } +/* Errata IPBUNIXTX-39300 */ +static inline bool +roc_errata_nix_assign_incorrect_qint(void) +{ + return (roc_model_is_cn10ka_a0() || roc_model_is_cnf10ka_a0() || + roc_model_is_cnf10kb_a0() || roc_model_is_cn10ka_a1()); +} + #endif /* _ROC_ERRATA_H_ */ diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 464ee0b984..21bfe7d498 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -1103,11 +1103,8 @@ sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum, aq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR); /* Many to one reduction */ - /* Assigning QINT 0 to all the SQs, an errata exists where NIXTX can - * send incorrect QINT_IDX when reporting queue interrupt (QINT). This - * might result in software missing the interrupt. - */ - aq->sq.qint_idx = 0; + aq->sq.qint_idx = sq->qid % nix->qints; + return 0; } @@ -1237,11 +1234,15 @@ sq_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum, uint16_t sm aq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR); aq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR); - /* Assigning QINT 0 to all the SQs, an errata exists where NIXTX can - * send incorrect QINT_IDX when reporting queue interrupt (QINT). This - * might result in software missing the interrupt. - */ - aq->sq.qint_idx = 0; + /* Many to one reduction */ + aq->sq.qint_idx = sq->qid % nix->qints; + if (roc_errata_nix_assign_incorrect_qint()) { + /* Assigning QINT 0 to all the SQs, an errata exists where NIXTX can + * send incorrect QINT_IDX when reporting queue interrupt (QINT). This + * might result in software missing the interrupt. + */ + aq->sq.qint_idx = 0; + } return 0; } -- 2.25.1