From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 137FD41DC3; Fri, 3 Mar 2023 09:12:23 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0BCB842D52; Fri, 3 Mar 2023 09:11:34 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id AA8B342D52 for ; Fri, 3 Mar 2023 09:11:32 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3234WwRa024923 for ; Fri, 3 Mar 2023 00:11:32 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=G3P35ufpymPatnvddtsrx5dMoWoTmSXvpUWIzY6VJrg=; b=eG6KA0vppgaRgF9WAIHnA6sqPkFYZe+jVDgvRWuvKgF0e7V5yatNufZOVH7/LkVpL0Gn 3PZLvqRI6k8Z2cI99X/KJ7ROBP+8wPobPJ7ZZFnRghX+NGS+fKgS2DhGP3o1Sp7tus3O CsqJXGyj7UVojjQ6y4UiZ8tyIjcQm/FvghMlUpEsnsEkoMu/QpKnaOgVUSlpxPh1JAvn tVSxdSMmCvXOhWbsFeedyMN/I0VLGIWJ+Dsn7KH9EO+GHw1ZIL8r6/jZ68gRIisvrBf8 /BaRXrtLjWDVFXL5WTyjydczYl4AKQxNau1f4e7XZha+zFo+fExy6BeWZ/Z+YefsILGS Ew== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3p1wr9xbm5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 03 Mar 2023 00:11:32 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 3 Mar 2023 00:11:29 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 3 Mar 2023 00:11:29 -0800 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 6BCE93F7052; Fri, 3 Mar 2023 00:11:24 -0800 (PST) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 14/15] common/cnxk: add memory clobber to steor and ldeor Date: Fri, 3 Mar 2023 13:40:12 +0530 Message-ID: <20230303081013.589868-14-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303081013.589868-1-ndabilpuram@marvell.com> References: <20230303081013.589868-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: tW23ymKlqSymdJaW-Ub4lj29i3k6EQvn X-Proofpoint-GUID: tW23ymKlqSymdJaW-Ub4lj29i3k6EQvn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-03_01,2023-03-02_02,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org To avoid compiler reordering stores to LMT line and ldeor, add clobber attribute to ldeor, steor etc. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_io.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/roc_io.h b/drivers/common/cnxk/roc_io.h index 1e5c1f8c04..af1a10cd66 100644 --- a/drivers/common/cnxk/roc_io.h +++ b/drivers/common/cnxk/roc_io.h @@ -130,7 +130,8 @@ roc_lmt_submit_ldeor(plt_iova_t io_address) asm volatile(PLT_CPU_FEATURE_PREAMBLE "ldeor xzr, %x[rf], [%[rs]]" : [rf] "=r"(result) - : [rs] "r"(io_address)); + : [rs] "r"(io_address) + : "memory"); return result; } @@ -141,7 +142,8 @@ roc_lmt_submit_ldeorl(plt_iova_t io_address) asm volatile(PLT_CPU_FEATURE_PREAMBLE "ldeorl xzr,%x[rf],[%[rs]]" : [rf] "=r"(result) - : [rs] "r"(io_address)); + : [rs] "r"(io_address) + : "memory"); return result; } @@ -150,7 +152,8 @@ roc_lmt_submit_steor(uint64_t data, plt_iova_t io_address) { asm volatile(PLT_CPU_FEATURE_PREAMBLE "steor %x[d], [%[rs]]" ::[d] "r"(data), - [rs] "r"(io_address)); + [rs] "r"(io_address) + : "memory"); } static __plt_always_inline void @@ -158,7 +161,8 @@ roc_lmt_submit_steorl(uint64_t data, plt_iova_t io_address) { asm volatile(PLT_CPU_FEATURE_PREAMBLE "steorl %x[d], [%[rs]]" ::[d] "r"(data), - [rs] "r"(io_address)); + [rs] "r"(io_address) + : "memory"); } static __plt_always_inline void -- 2.25.1