From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E95C041DD0; Fri, 10 Mar 2023 09:23:52 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3F58042F98; Fri, 10 Mar 2023 09:21:07 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7432A42D1A for ; Fri, 10 Mar 2023 09:20:34 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32A7uIdJ021875 for ; Fri, 10 Mar 2023 00:20:33 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=xeAijMZVsgE559mrWl2bAGVKpgMsX1wl/FCZ2hK+wEE=; b=V4vgMmXMLkVRr76YCjHW9OtFMwUND0sHoGE7Om0Z3qNYpmeJ2deR1FBc2iU782h4SZBE 14uyXIt5fQct8ZS4vU2b8UYTdjIa5X0UBnK8v7+Ui49IXp6ghypj26xgvlrc3P56WXrH lBQEi5ZpimUaBbYtdpnjutyX9KYSQiUTXvCYOScutRYfaKsssmPoppFN8D/hJs/kbCUZ 69oLSYc3J2FTqeY9QT/aarQAkHOseuvrjNoi0l9hCUOgtkE8ONOZKI1YhSuakm1k+xsr TId+R2QfwJY6nnnzexXqt0WtPUvBajjPria1DKwtYjVM64rEm7ZYK1wdmteENmTf7Y42 Ig== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3p80k782tf-18 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 10 Mar 2023 00:20:33 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 10 Mar 2023 00:20:24 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 10 Mar 2023 00:20:24 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id A35E13F7093; Fri, 10 Mar 2023 00:20:23 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , , , Subject: [PATCH v6 32/39] ml/cnxk: enable support to get xstats in cycles Date: Fri, 10 Mar 2023 00:20:08 -0800 Message-ID: <20230310082015.20200-33-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230310082015.20200-1-syalavarthi@marvell.com> References: <20221208200220.20267-1-syalavarthi@marvell.com> <20230310082015.20200-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: bDWOBLQuV-LXdEnZiq4VA5zUr5BG5VnF X-Proofpoint-ORIG-GUID: bDWOBLQuV-LXdEnZiq4VA5zUr5BG5VnF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-10_02,2023-03-09_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enabled support to retrieve xstats in either cycles or ns. Access to sclk is enabled only if an RVU device is probed during initialization. Driver would return the xstats in nanoseconds only when an RVU device is probed, else would fallback to cycles. Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_ops.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c index 880bb6a5a9..5689fbfcb2 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.c +++ b/drivers/ml/cnxk/cn10k_ml_ops.c @@ -394,6 +394,8 @@ cn10k_ml_model_xstat_get(struct rte_ml_dev *dev, uint16_t model_id, enum cn10k_ml_model_xstats_type type) { struct cn10k_ml_model *model; + uint16_t rclk_freq; /* MHz */ + uint16_t sclk_freq; /* MHz */ uint64_t count = 0; uint64_t value; uint32_t qp_id; @@ -425,6 +427,10 @@ cn10k_ml_model_xstat_get(struct rte_ml_dev *dev, uint16_t model_id, value = 0; } + roc_clk_freq_get(&rclk_freq, &sclk_freq); + if (sclk_freq != 0) /* return in ns */ + value = (value * 1000ULL) / sclk_freq; + return value; } @@ -863,6 +869,8 @@ cn10k_ml_dev_xstats_names_get(struct rte_ml_dev *dev, struct rte_ml_dev_xstats_m struct rte_ml_dev_info dev_info; struct cn10k_ml_model *model; struct cn10k_ml_dev *mldev; + uint16_t rclk_freq; + uint16_t sclk_freq; uint32_t model_id; uint32_t count; uint32_t type; @@ -878,6 +886,7 @@ cn10k_ml_dev_xstats_names_get(struct rte_ml_dev *dev, struct rte_ml_dev_xstats_m /* Model xstats names */ count = 0; cn10k_ml_dev_info_get(dev, &dev_info); + roc_clk_freq_get(&rclk_freq, &sclk_freq); for (id = 0; id < PLT_DIM(cn10k_ml_model_xstats_table) * dev_info.max_models; id++) { model_id = id / PLT_DIM(cn10k_ml_model_xstats_table); @@ -889,8 +898,14 @@ cn10k_ml_dev_xstats_names_get(struct rte_ml_dev *dev, struct rte_ml_dev_xstats_m xstats_map[count].id = id; type = id % PLT_DIM(cn10k_ml_model_xstats_table); - snprintf(xstats_map[count].name, RTE_ML_STR_MAX, "%s-%s-cycles", - model->metadata.model.name, cn10k_ml_model_xstats_table[type].name); + if (sclk_freq == 0) + snprintf(xstats_map[count].name, RTE_ML_STR_MAX, "%s-%s-cycles", + model->metadata.model.name, + cn10k_ml_model_xstats_table[type].name); + else + snprintf(xstats_map[count].name, RTE_ML_STR_MAX, "%s-%s-ns", + model->metadata.model.name, + cn10k_ml_model_xstats_table[type].name); count++; if (count == size) -- 2.17.1