From: Srikanth Yalavarthi <syalavarthi@marvell.com>
To: Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>
Cc: <dev@dpdk.org>, <syalavarthi@marvell.com>,
<sshankarnara@marvell.com>, <jerinj@marvell.com>
Subject: [PATCH 1/1] doc: add ML to list of cnxk platform blocks
Date: Mon, 13 Mar 2023 10:40:15 -0700 [thread overview]
Message-ID: <20230313174015.13602-1-syalavarthi@marvell.com> (raw)
Add ML to the list of platform hardware accelerator blocks.
Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
---
doc/guides/platform/cnxk.rst | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
index aadd60b5d4..1956cc31d8 100644
--- a/doc/guides/platform/cnxk.rst
+++ b/doc/guides/platform/cnxk.rst
@@ -76,6 +76,8 @@ DPDK subsystem.
+---+-----+--------------------------------------------------------------+
| 12| GPIO| rte_rawdev |
+---+-----+--------------------------------------------------------------+
+ | 12| ML | rte_mldev |
+ +---+-----+--------------------------------------------------------------+
PF0 is called the administrative / admin function (AF) and has exclusive
privileges to provision RVU functional block's LFs to each of the PF/VF.
@@ -165,6 +167,9 @@ This section lists dataplane H/W block(s) available in cnxk SoC.
#. **Regex Device Driver**
See :doc:`../regexdevs/cn9k` for REE Regex device driver information.
+#. **ML Device Driver**
+ See :doc:`../mldevs/cnxk` for Machine Learning device driver information.
+
Procedure to Setup Platform
---------------------------
--
2.17.1
next reply other threads:[~2023-03-13 17:40 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-13 17:40 Srikanth Yalavarthi [this message]
2023-03-14 6:30 ` Jerin Jacob
2023-03-14 6:45 ` [PATCH v2 1/1] doc: fix cnxk platform HW accelerator blocks list Srikanth Yalavarthi
2023-03-15 5:53 ` Jerin Jacob
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