* [PATCH 1/1] doc: add ML to list of cnxk platform blocks
@ 2023-03-13 17:40 Srikanth Yalavarthi
2023-03-14 6:30 ` Jerin Jacob
2023-03-14 6:45 ` [PATCH v2 1/1] doc: fix cnxk platform HW accelerator blocks list Srikanth Yalavarthi
0 siblings, 2 replies; 4+ messages in thread
From: Srikanth Yalavarthi @ 2023-03-13 17:40 UTC (permalink / raw)
To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
Cc: dev, syalavarthi, sshankarnara, jerinj
Add ML to the list of platform hardware accelerator blocks.
Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
---
doc/guides/platform/cnxk.rst | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
index aadd60b5d4..1956cc31d8 100644
--- a/doc/guides/platform/cnxk.rst
+++ b/doc/guides/platform/cnxk.rst
@@ -76,6 +76,8 @@ DPDK subsystem.
+---+-----+--------------------------------------------------------------+
| 12| GPIO| rte_rawdev |
+---+-----+--------------------------------------------------------------+
+ | 12| ML | rte_mldev |
+ +---+-----+--------------------------------------------------------------+
PF0 is called the administrative / admin function (AF) and has exclusive
privileges to provision RVU functional block's LFs to each of the PF/VF.
@@ -165,6 +167,9 @@ This section lists dataplane H/W block(s) available in cnxk SoC.
#. **Regex Device Driver**
See :doc:`../regexdevs/cn9k` for REE Regex device driver information.
+#. **ML Device Driver**
+ See :doc:`../mldevs/cnxk` for Machine Learning device driver information.
+
Procedure to Setup Platform
---------------------------
--
2.17.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/1] doc: add ML to list of cnxk platform blocks
2023-03-13 17:40 [PATCH 1/1] doc: add ML to list of cnxk platform blocks Srikanth Yalavarthi
@ 2023-03-14 6:30 ` Jerin Jacob
2023-03-14 6:45 ` [PATCH v2 1/1] doc: fix cnxk platform HW accelerator blocks list Srikanth Yalavarthi
1 sibling, 0 replies; 4+ messages in thread
From: Jerin Jacob @ 2023-03-14 6:30 UTC (permalink / raw)
To: Srikanth Yalavarthi
Cc: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao,
dev, sshankarnara, jerinj
On Mon, Mar 13, 2023 at 11:10 PM Srikanth Yalavarthi
<syalavarthi@marvell.com> wrote:
>
> Add ML to the list of platform hardware accelerator blocks.
>
> Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
> ---
> doc/guides/platform/cnxk.rst | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
> index aadd60b5d4..1956cc31d8 100644
> --- a/doc/guides/platform/cnxk.rst
> +++ b/doc/guides/platform/cnxk.rst
> @@ -76,6 +76,8 @@ DPDK subsystem.
> +---+-----+--------------------------------------------------------------+
> | 12| GPIO| rte_rawdev |
> +---+-----+--------------------------------------------------------------+
> + | 12| ML | rte_mldev |
> + +---+-----+--------------------------------------------------------------
# It should be 13 instead of 12.
# Also, please add fixes: tags and change subject accordingly
With above changes:
Acked-by: Jerin Jacob <jerinj@marvell.com>
+
>
> PF0 is called the administrative / admin function (AF) and has exclusive
> privileges to provision RVU functional block's LFs to each of the PF/VF.
> @@ -165,6 +167,9 @@ This section lists dataplane H/W block(s) available in cnxk SoC.
> #. **Regex Device Driver**
> See :doc:`../regexdevs/cn9k` for REE Regex device driver information.
>
> +#. **ML Device Driver**
> + See :doc:`../mldevs/cnxk` for Machine Learning device driver information.
> +
> Procedure to Setup Platform
> ---------------------------
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v2 1/1] doc: fix cnxk platform HW accelerator blocks list
2023-03-13 17:40 [PATCH 1/1] doc: add ML to list of cnxk platform blocks Srikanth Yalavarthi
2023-03-14 6:30 ` Jerin Jacob
@ 2023-03-14 6:45 ` Srikanth Yalavarthi
2023-03-15 5:53 ` Jerin Jacob
1 sibling, 1 reply; 4+ messages in thread
From: Srikanth Yalavarthi @ 2023-03-14 6:45 UTC (permalink / raw)
To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao,
Srikanth Yalavarthi, Prince Takkar
Cc: dev, sshankarnara, jerinj
Add ML to the list of platform hardware accelerator blocks,
and added reference to ML device driver.
Fixes: fe83ffd9ec2e ("ml/cnxk: add skeleton")
Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
---
v2:
* Updated fixes and commit message
* Updated device table index
doc/guides/platform/cnxk.rst | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
index aadd60b5d4..4a1966c66b 100644
--- a/doc/guides/platform/cnxk.rst
+++ b/doc/guides/platform/cnxk.rst
@@ -76,6 +76,8 @@ DPDK subsystem.
+---+-----+--------------------------------------------------------------+
| 12| GPIO| rte_rawdev |
+---+-----+--------------------------------------------------------------+
+ | 13| ML | rte_mldev |
+ +---+-----+--------------------------------------------------------------+
PF0 is called the administrative / admin function (AF) and has exclusive
privileges to provision RVU functional block's LFs to each of the PF/VF.
@@ -165,6 +167,9 @@ This section lists dataplane H/W block(s) available in cnxk SoC.
#. **Regex Device Driver**
See :doc:`../regexdevs/cn9k` for REE Regex device driver information.
+#. **ML Device Driver**
+ See :doc:`../mldevs/cnxk` for Machine Learning device driver information.
+
Procedure to Setup Platform
---------------------------
--
2.17.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 1/1] doc: fix cnxk platform HW accelerator blocks list
2023-03-14 6:45 ` [PATCH v2 1/1] doc: fix cnxk platform HW accelerator blocks list Srikanth Yalavarthi
@ 2023-03-15 5:53 ` Jerin Jacob
0 siblings, 0 replies; 4+ messages in thread
From: Jerin Jacob @ 2023-03-15 5:53 UTC (permalink / raw)
To: Srikanth Yalavarthi
Cc: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao,
Prince Takkar, dev, sshankarnara, jerinj
On Tue, Mar 14, 2023 at 12:15 PM Srikanth Yalavarthi
<syalavarthi@marvell.com> wrote:
>
> Add ML to the list of platform hardware accelerator blocks,
> and added reference to ML device driver.
>
> Fixes: fe83ffd9ec2e ("ml/cnxk: add skeleton")
>
> Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
> Acked-by: Jerin Jacob <jerinj@marvell.com>
Applied to dpdk-next-net-mrvl/for-next-net. Thanks
>
> ---
>
> v2:
> * Updated fixes and commit message
> * Updated device table index
>
> doc/guides/platform/cnxk.rst | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
> index aadd60b5d4..4a1966c66b 100644
> --- a/doc/guides/platform/cnxk.rst
> +++ b/doc/guides/platform/cnxk.rst
> @@ -76,6 +76,8 @@ DPDK subsystem.
> +---+-----+--------------------------------------------------------------+
> | 12| GPIO| rte_rawdev |
> +---+-----+--------------------------------------------------------------+
> + | 13| ML | rte_mldev |
> + +---+-----+--------------------------------------------------------------+
>
> PF0 is called the administrative / admin function (AF) and has exclusive
> privileges to provision RVU functional block's LFs to each of the PF/VF.
> @@ -165,6 +167,9 @@ This section lists dataplane H/W block(s) available in cnxk SoC.
> #. **Regex Device Driver**
> See :doc:`../regexdevs/cn9k` for REE Regex device driver information.
>
> +#. **ML Device Driver**
> + See :doc:`../mldevs/cnxk` for Machine Learning device driver information.
> +
> Procedure to Setup Platform
> ---------------------------
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-03-13 17:40 [PATCH 1/1] doc: add ML to list of cnxk platform blocks Srikanth Yalavarthi
2023-03-14 6:30 ` Jerin Jacob
2023-03-14 6:45 ` [PATCH v2 1/1] doc: fix cnxk platform HW accelerator blocks list Srikanth Yalavarthi
2023-03-15 5:53 ` Jerin Jacob
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