From: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
To: <dev@dpdk.org>
Cc: <matan@nvidia.com>, <rasland@nvidia.com>, <orika@nvidia.com>
Subject: [PATCH] doc: update mlx5 limitations on ESP header match
Date: Wed, 22 Mar 2023 17:07:20 +0200 [thread overview]
Message-ID: <20230322150720.25722-1-viacheslavo@nvidia.com> (raw)
The match on ESP header is supported over PF only.
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
doc/guides/nics/mlx5.rst | 2 ++
1 file changed, 2 insertions(+)
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 7960a42e9c..1698831c5f 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -289,6 +289,8 @@ Limitations
- When using DV/Verbs flow engine (``dv_flow_en`` = 1/0 respectively),
match on SPI field in ESP header for group 0 is supported from ConnectX-7.
+- Matching on SPI field in ESP header is supported over the PF only.
+
- Flex item:
- Hardware support: **NVIDIA BlueField-2** and **NVIDIA BlueField-3**.
--
2.18.1
next reply other threads:[~2023-03-22 15:07 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-22 15:07 Viacheslav Ovsiienko [this message]
2023-03-23 19:41 ` Raslan Darawsheh
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