From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DA5BA428CE; Tue, 4 Apr 2023 16:19:10 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4B8C541153; Tue, 4 Apr 2023 16:19:06 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id E64E140A7E for ; Tue, 4 Apr 2023 16:19:03 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 334Cv92p019623 for ; Tue, 4 Apr 2023 07:19:03 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=pfpt0220; bh=w7K27PEm4z4naR1sBZyfEuQyuwHu/v6AC7Y/74zGS4Q=; b=SEyjD44byOHQcxjN/W4XA7z4/+HxNs5gOgGQx5LUKDqgPYqVivw3f5R0Gyxvt156KD2K Bt+CVcqNBKKBt/sqnX23e4HnIGDeK2hmTNMxFfG7tiUnBr4FVbm3X8CL2sqvRPrk5Pvp lMOjN6MtnbFZzl6YaJrU3MT1U5GrHdn3EaQIkAQJpLMPfxsub0yTvCZTkaMn2cRcicq0 aA73AEUXmIC5G6XO/BnjCVMT1/7K0m0czhUyYq752QjpLGieip/3I2CS60DDg4RtLryu nsRhKyy4pghhTqEunSQdZ0YrbJsZVKaUZxkujx+3S0S9+ZkIRQdBNjUKszfaGvmIVflJ +g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ppm4qw0vx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 04 Apr 2023 07:19:03 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 4 Apr 2023 07:19:01 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 4 Apr 2023 07:19:01 -0700 Received: from localhost.marvell.com (unknown [10.106.27.249]) by maili.marvell.com (Postfix) with ESMTP id 2ED645B6931; Tue, 4 Apr 2023 07:19:01 -0700 (PDT) From: Sathesh Edara To: , , , "Radha Mohan Chintakuntla" , Veerasenareddy Burru CC: Subject: [PATCH v1 1/9] net/octeon_ep: support cnf95n and cnf95o SoC Date: Tue, 4 Apr 2023 07:18:46 -0700 Message-ID: <20230404141855.1025625-2-sedara@marvell.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230404141855.1025625-1-sedara@marvell.com> References: <20230404141855.1025625-1-sedara@marvell.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: vdFopNG2dqqQl8r0PJ3tCw40YexfdaxN X-Proofpoint-GUID: vdFopNG2dqqQl8r0PJ3tCw40YexfdaxN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-04_06,2023-04-04_04,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds the required functionality in the Octeon endpoint driver to support the cnf95n and cnf95o endpoint device. Signed-off-by: Sathesh Edara --- drivers/net/octeon_ep/otx2_ep_vf.h | 2 ++ drivers/net/octeon_ep/otx_ep_ethdev.c | 13 +++++++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/net/octeon_ep/otx2_ep_vf.h b/drivers/net/octeon_ep/otx2_ep_vf.h index 757eeae9f0..8f00acd737 100644 --- a/drivers/net/octeon_ep/otx2_ep_vf.h +++ b/drivers/net/octeon_ep/otx2_ep_vf.h @@ -115,6 +115,8 @@ #define PCI_DEVID_CN9K_EP_NET_VF 0xB203 /* OCTEON 9 EP mode */ #define PCI_DEVID_CN98XX_EP_NET_VF 0xB103 +#define PCI_DEVID_CNF95N_EP_NET_VF 0xB403 +#define PCI_DEVID_CNF95O_EP_NET_VF 0xB603 int otx2_ep_vf_setup_device(struct otx_ep_device *sdpvf); diff --git a/drivers/net/octeon_ep/otx_ep_ethdev.c b/drivers/net/octeon_ep/otx_ep_ethdev.c index f43db1e398..24f62c3e49 100644 --- a/drivers/net/octeon_ep/otx_ep_ethdev.c +++ b/drivers/net/octeon_ep/otx_ep_ethdev.c @@ -105,6 +105,8 @@ otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf) break; case PCI_DEVID_CN9K_EP_NET_VF: case PCI_DEVID_CN98XX_EP_NET_VF: + case PCI_DEVID_CNF95N_EP_NET_VF: + case PCI_DEVID_CNF95O_EP_NET_VF: otx_epvf->chip_id = dev_id; ret = otx2_ep_vf_setup_device(otx_epvf); otx_epvf->fn_list.disable_io_queues(otx_epvf); @@ -144,7 +146,9 @@ otx_epdev_init(struct otx_ep_device *otx_epvf) if (otx_epvf->chip_id == PCI_DEVID_OCTEONTX_EP_VF) otx_epvf->eth_dev->tx_pkt_burst = &otx_ep_xmit_pkts; else if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF || - otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF) + otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF || + otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF || + otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF) otx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts; else if (otx_epvf->chip_id == PCI_DEVID_CNXK_EP_NET_VF) otx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts; @@ -494,7 +498,10 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev) otx_epvf->pdev = pdev; otx_epdev_init(otx_epvf); - if (pdev->id.device_id == PCI_DEVID_CN9K_EP_NET_VF) + if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF || + otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF || + otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF || + otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF) otx_epvf->pkind = SDP_OTX2_PKIND_FS0; else otx_epvf->pkind = SDP_PKIND; @@ -524,6 +531,8 @@ static const struct rte_pci_id pci_id_otx_ep_map[] = { { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX_EP_VF) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN9K_EP_NET_VF) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN98XX_EP_NET_VF) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF95N_EP_NET_VF) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF95O_EP_NET_VF) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_EP_NET_VF) }, { .vendor_id = 0, /* sentinel */ } }; -- 2.31.1