From: Sathesh Edara <sedara@marvell.com>
To: <sburla@marvell.com>, <jerinj@marvell.com>, <sedara@marvell.com>,
"Radha Mohan Chintakuntla" <radhac@marvell.com>,
Veerasenareddy Burru <vburru@marvell.com>
Cc: <dev@dpdk.org>
Subject: [PATCH v1 3/9] net/octeon_ep: support error propagation
Date: Tue, 4 Apr 2023 07:18:48 -0700 [thread overview]
Message-ID: <20230404141855.1025625-4-sedara@marvell.com> (raw)
In-Reply-To: <20230404141855.1025625-1-sedara@marvell.com>
This patch adds detection of loop limits being
hit, and propagate errors up the call chain when
this happens.
Signed-off-by: Sathesh Edara <sedara@marvell.com>
---
drivers/net/octeon_ep/cnxk_ep_vf.c | 51 +++++++++++--------
drivers/net/octeon_ep/otx2_ep_vf.c | 49 ++++++++++--------
drivers/net/octeon_ep/otx_ep_common.h | 6 +--
drivers/net/octeon_ep/otx_ep_ethdev.c | 27 +++++++---
drivers/net/octeon_ep/otx_ep_rxtx.c | 51 +++++++++----------
drivers/net/octeon_ep/otx_ep_vf.c | 71 +++++++++++++++++++--------
6 files changed, 155 insertions(+), 100 deletions(-)
diff --git a/drivers/net/octeon_ep/cnxk_ep_vf.c b/drivers/net/octeon_ep/cnxk_ep_vf.c
index 3427fb213b..1a92887109 100644
--- a/drivers/net/octeon_ep/cnxk_ep_vf.c
+++ b/drivers/net/octeon_ep/cnxk_ep_vf.c
@@ -47,36 +47,43 @@ cnxk_ep_vf_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)
oct_ep_write64(reg_val, otx_ep->hw_addr + CNXK_EP_R_OUT_CONTROL(q_no));
}
-static void
+static int
cnxk_ep_vf_setup_global_input_regs(struct otx_ep_device *otx_ep)
{
uint64_t q_no = 0ull;
for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
cnxk_ep_vf_setup_global_iq_reg(otx_ep, q_no);
+ return 0;
}
-static void
+static int
cnxk_ep_vf_setup_global_output_regs(struct otx_ep_device *otx_ep)
{
uint32_t q_no;
for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
cnxk_ep_vf_setup_global_oq_reg(otx_ep, q_no);
+ return 0;
}
-static void
+static int
cnxk_ep_vf_setup_device_regs(struct otx_ep_device *otx_ep)
{
- cnxk_ep_vf_setup_global_input_regs(otx_ep);
- cnxk_ep_vf_setup_global_output_regs(otx_ep);
+ int ret;
+
+ ret = cnxk_ep_vf_setup_global_input_regs(otx_ep);
+ if (ret)
+ return ret;
+ ret = cnxk_ep_vf_setup_global_output_regs(otx_ep);
+ return ret;
}
-static void
+static int
cnxk_ep_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
{
struct otx_ep_instr_queue *iq = otx_ep->instr_queue[iq_no];
- uint64_t loop = OTX_EP_BUSY_LOOP_COUNT;
+ int loop = OTX_EP_BUSY_LOOP_COUNT;
volatile uint64_t reg_val = 0ull;
reg_val = oct_ep_read64(otx_ep->hw_addr + CNXK_EP_R_IN_CONTROL(iq_no));
@@ -91,9 +98,9 @@ cnxk_ep_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
} while ((!(reg_val & CNXK_EP_R_IN_CTL_IDLE)) && loop--);
}
- if (!loop) {
+ if (loop < 0) {
otx_ep_err("IDLE bit is not set\n");
- return;
+ return -EIO;
}
/* Write the start of the input queue's ring and its size */
@@ -115,9 +122,9 @@ cnxk_ep_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
rte_delay_ms(1);
} while (reg_val != 0 && loop--);
- if (!loop) {
+ if (loop < 0) {
otx_ep_err("INST CNT REGISTER is not zero\n");
- return;
+ return -EIO;
}
/* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR
@@ -125,14 +132,15 @@ cnxk_ep_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
*/
oct_ep_write64(OTX_EP_CLEAR_SDP_IN_INT_LVLS,
otx_ep->hw_addr + CNXK_EP_R_IN_INT_LEVELS(iq_no));
+ return 0;
}
-static void
+static int
cnxk_ep_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
{
volatile uint64_t reg_val = 0ull;
uint64_t oq_ctl = 0ull;
- uint64_t loop = OTX_EP_BUSY_LOOP_COUNT;
+ int loop = OTX_EP_BUSY_LOOP_COUNT;
struct otx_ep_droq *droq = otx_ep->droq[oq_no];
/* Wait on IDLE to set to 1, supposed to configure BADDR
@@ -145,9 +153,9 @@ cnxk_ep_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
rte_delay_ms(1);
}
- if (!loop) {
+ if (loop < 0) {
otx_ep_err("OUT CNT REGISTER value is zero\n");
- return;
+ return -EIO;
}
oct_ep_write64(droq->desc_ring_dma, otx_ep->hw_addr + CNXK_EP_R_OUT_SLIST_BADDR(oq_no));
@@ -181,9 +189,9 @@ cnxk_ep_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
rte_delay_ms(1);
}
- if (!loop) {
+ if (loop < 0) {
otx_ep_err("Packets credit register value is not cleared\n");
- return;
+ return -EIO;
}
otx_ep_dbg("SDP_R[%d]_credit:%x", oq_no, rte_read32(droq->pkts_credit_reg));
@@ -201,18 +209,19 @@ cnxk_ep_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
rte_delay_ms(1);
}
- if (!loop) {
+ if (loop < 0) {
otx_ep_err("Packets sent register value is not cleared\n");
- return;
+ return -EIO;
}
otx_ep_dbg("SDP_R[%d]_sent: %x", oq_no, rte_read32(droq->pkts_sent_reg));
+ return 0;
}
static int
cnxk_ep_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
{
- uint64_t loop = OTX_EP_BUSY_LOOP_COUNT;
+ int loop = OTX_EP_BUSY_LOOP_COUNT;
uint64_t reg_val = 0ull;
/* Resetting doorbells during IQ enabling also to handle abrupt
@@ -225,7 +234,7 @@ cnxk_ep_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
rte_delay_ms(1);
}
- if (!loop) {
+ if (loop < 0) {
otx_ep_err("INSTR DBELL not coming back to 0\n");
return -EIO;
}
diff --git a/drivers/net/octeon_ep/otx2_ep_vf.c b/drivers/net/octeon_ep/otx2_ep_vf.c
index 3c9a70157e..3ffc7275c7 100644
--- a/drivers/net/octeon_ep/otx2_ep_vf.c
+++ b/drivers/net/octeon_ep/otx2_ep_vf.c
@@ -49,32 +49,39 @@ otx2_vf_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)
oct_ep_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
}
-static void
+static int
otx2_vf_setup_global_input_regs(struct otx_ep_device *otx_ep)
{
uint64_t q_no = 0ull;
for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
otx2_vf_setup_global_iq_reg(otx_ep, q_no);
+ return 0;
}
-static void
+static int
otx2_vf_setup_global_output_regs(struct otx_ep_device *otx_ep)
{
uint32_t q_no;
for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
otx2_vf_setup_global_oq_reg(otx_ep, q_no);
+ return 0;
}
-static void
+static int
otx2_vf_setup_device_regs(struct otx_ep_device *otx_ep)
{
- otx2_vf_setup_global_input_regs(otx_ep);
- otx2_vf_setup_global_output_regs(otx_ep);
+ int ret;
+
+ ret = otx2_vf_setup_global_input_regs(otx_ep);
+ if (ret)
+ return ret;
+ ret = otx2_vf_setup_global_output_regs(otx_ep);
+ return ret;
}
-static void
+static int
otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
{
struct otx_ep_instr_queue *iq = otx_ep->instr_queue[iq_no];
@@ -92,9 +99,9 @@ otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
} while ((!(reg_val & SDP_VF_R_IN_CTL_IDLE)) && loop--);
}
- if (!loop) {
+ if (loop < 0) {
otx_ep_err("IDLE bit is not set\n");
- return;
+ return -EIO;
}
/* Write the start of the input queue's ring and its size */
@@ -115,9 +122,9 @@ otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
rte_write32(reg_val, iq->inst_cnt_reg);
} while (reg_val != 0 && loop--);
- if (!loop) {
+ if (loop < 0) {
otx_ep_err("INST CNT REGISTER is not zero\n");
- return;
+ return -EIO;
}
/* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR
@@ -125,14 +132,15 @@ otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
*/
oct_ep_write64(OTX_EP_CLEAR_SDP_IN_INT_LVLS,
otx_ep->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));
+ return 0;
}
-static void
+static int
otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
{
volatile uint64_t reg_val = 0ull;
uint64_t oq_ctl = 0ull;
- uint64_t loop = OTX_EP_BUSY_LOOP_COUNT;
+ int loop = OTX_EP_BUSY_LOOP_COUNT;
struct otx_ep_droq *droq = otx_ep->droq[oq_no];
/* Wait on IDLE to set to 1, supposed to configure BADDR
@@ -145,9 +153,9 @@ otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
rte_delay_ms(1);
}
- if (!loop) {
+ if (loop < 0) {
otx_ep_err("OUT CNT REGISTER value is zero\n");
- return;
+ return -EIO;
}
oct_ep_write64(droq->desc_ring_dma, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_BADDR(oq_no));
@@ -181,9 +189,9 @@ otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
rte_delay_ms(1);
}
- if (!loop) {
+ if (loop < 0) {
otx_ep_err("Packets credit register value is not cleared\n");
- return;
+ return -EIO;
}
otx_ep_dbg("SDP_R[%d]_credit:%x", oq_no, rte_read32(droq->pkts_credit_reg));
@@ -200,17 +208,18 @@ otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
rte_delay_ms(1);
}
- if (!loop) {
+ if (loop < 0) {
otx_ep_err("Packets sent register value is not cleared\n");
- return;
+ return -EIO;
}
otx_ep_dbg("SDP_R[%d]_sent: %x", oq_no, rte_read32(droq->pkts_sent_reg));
+ return 0;
}
static int
otx2_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
{
- uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
+ int loop = SDP_VF_BUSY_LOOP_COUNT;
uint64_t reg_val = 0ull;
/* Resetting doorbells during IQ enabling also to handle abrupt
@@ -223,7 +232,7 @@ otx2_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
rte_delay_ms(1);
}
- if (!loop) {
+ if (loop < 0) {
otx_ep_err("INSTR DBELL not coming back to 0\n");
return -EIO;
}
diff --git a/drivers/net/octeon_ep/otx_ep_common.h b/drivers/net/octeon_ep/otx_ep_common.h
index e4c92270d4..479bb1a1a0 100644
--- a/drivers/net/octeon_ep/otx_ep_common.h
+++ b/drivers/net/octeon_ep/otx_ep_common.h
@@ -394,11 +394,11 @@ struct otx_ep_sriov_info {
/* Required functions for each VF device */
struct otx_ep_fn_list {
- void (*setup_iq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);
+ int (*setup_iq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);
- void (*setup_oq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);
+ int (*setup_oq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);
- void (*setup_device_regs)(struct otx_ep_device *otx_ep);
+ int (*setup_device_regs)(struct otx_ep_device *otx_ep);
int (*enable_io_queues)(struct otx_ep_device *otx_ep);
void (*disable_io_queues)(struct otx_ep_device *otx_ep);
diff --git a/drivers/net/octeon_ep/otx_ep_ethdev.c b/drivers/net/octeon_ep/otx_ep_ethdev.c
index b23d52ff84..5677a2d6a6 100644
--- a/drivers/net/octeon_ep/otx_ep_ethdev.c
+++ b/drivers/net/octeon_ep/otx_ep_ethdev.c
@@ -151,13 +151,17 @@ otx_epdev_init(struct otx_ep_device *otx_epvf)
else if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF ||
otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF ||
otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF ||
- otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF)
- otx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;
- else if (otx_epvf->chip_id == PCI_DEVID_CN10KA_EP_NET_VF ||
+ otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF ||
+ otx_epvf->chip_id == PCI_DEVID_CN10KA_EP_NET_VF ||
otx_epvf->chip_id == PCI_DEVID_CN10KB_EP_NET_VF ||
otx_epvf->chip_id == PCI_DEVID_CNF10KA_EP_NET_VF ||
- otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF)
+ otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF) {
otx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;
+ } else {
+ otx_ep_err("Invalid chip_id\n");
+ ret = -EINVAL;
+ goto setup_fail;
+ }
ethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf);
otx_epvf->max_rx_queues = ethdev_queues;
otx_epvf->max_tx_queues = ethdev_queues;
@@ -489,6 +493,7 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return 0;
+ rte_eth_copy_pci_info(eth_dev, pdev);
otx_epvf->eth_dev = eth_dev;
otx_epvf->port_id = eth_dev->data->port_id;
eth_dev->dev_ops = &otx_ep_eth_dev_ops;
@@ -503,7 +508,8 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)
otx_epvf->hw_addr = pdev->mem_resource[0].addr;
otx_epvf->pdev = pdev;
- otx_epdev_init(otx_epvf);
+ if (otx_epdev_init(otx_epvf))
+ return -ENOMEM;
if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF ||
otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF ||
otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF ||
@@ -511,11 +517,16 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)
otx_epvf->chip_id == PCI_DEVID_CN10KA_EP_NET_VF ||
otx_epvf->chip_id == PCI_DEVID_CN10KB_EP_NET_VF ||
otx_epvf->chip_id == PCI_DEVID_CNF10KA_EP_NET_VF ||
- otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF)
+ otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF) {
otx_epvf->pkind = SDP_OTX2_PKIND_FS0;
- else
+ otx_ep_info("using pkind %d\n", otx_epvf->pkind);
+ } else if (otx_epvf->chip_id == PCI_DEVID_OCTEONTX_EP_VF) {
otx_epvf->pkind = SDP_PKIND;
- otx_ep_info("using pkind %d\n", otx_epvf->pkind);
+ otx_ep_info("Using pkind %d.\n", otx_epvf->pkind);
+ } else {
+ otx_ep_err("Invalid chip id\n");
+ return -EINVAL;
+ }
return 0;
}
diff --git a/drivers/net/octeon_ep/otx_ep_rxtx.c b/drivers/net/octeon_ep/otx_ep_rxtx.c
index 6912ca2401..9712e6cce6 100644
--- a/drivers/net/octeon_ep/otx_ep_rxtx.c
+++ b/drivers/net/octeon_ep/otx_ep_rxtx.c
@@ -3,7 +3,7 @@
*/
#include <unistd.h>
-
+#include <assert.h>
#include <rte_eal.h>
#include <rte_mempool.h>
#include <rte_mbuf.h>
@@ -81,6 +81,7 @@ otx_ep_init_instr_queue(struct otx_ep_device *otx_ep, int iq_no, int num_descs,
const struct otx_ep_config *conf;
struct otx_ep_instr_queue *iq;
uint32_t q_size;
+ int ret;
conf = otx_ep->conf;
iq = otx_ep->instr_queue[iq_no];
@@ -140,7 +141,9 @@ otx_ep_init_instr_queue(struct otx_ep_device *otx_ep, int iq_no, int num_descs,
iq->iqcmd_64B = (conf->iq.instr_type == 64);
/* Set up IQ registers */
- otx_ep->fn_list.setup_iq_regs(otx_ep, iq_no);
+ ret = otx_ep->fn_list.setup_iq_regs(otx_ep, iq_no);
+ if (ret)
+ return ret;
return 0;
@@ -271,6 +274,7 @@ otx_ep_init_droq(struct otx_ep_device *otx_ep, uint32_t q_no,
uint32_t c_refill_threshold;
struct otx_ep_droq *droq;
uint32_t desc_ring_size;
+ int ret;
otx_ep_info("OQ[%d] Init start\n", q_no);
@@ -318,7 +322,9 @@ otx_ep_init_droq(struct otx_ep_device *otx_ep, uint32_t q_no,
droq->refill_threshold = c_refill_threshold;
/* Set up OQ registers */
- otx_ep->fn_list.setup_oq_regs(otx_ep, q_no);
+ ret = otx_ep->fn_list.setup_oq_regs(otx_ep, q_no);
+ if (ret)
+ return ret;
otx_ep->io_qmask.oq |= (1ull << q_no);
@@ -852,19 +858,15 @@ otx_ep_droq_read_packet(struct otx_ep_device *otx_ep,
* droq->pkts_pending);
*/
droq->stats.pkts_delayed_data++;
- while (retry && !info->length)
+ while (retry && !info->length) {
retry--;
+ rte_delay_us_block(50);
+ }
if (!retry && !info->length) {
otx_ep_err("OCTEON DROQ[%d]: read_idx: %d; Retry failed !!\n",
droq->q_no, droq->read_idx);
/* May be zero length packet; drop it */
- rte_pktmbuf_free(droq_pkt);
- droq->recv_buf_list[droq->read_idx] = NULL;
- droq->read_idx = otx_ep_incr_index(droq->read_idx, 1,
- droq->nb_desc);
- droq->stats.dropped_zlp++;
- droq->refill_count++;
- goto oq_read_fail;
+ assert(0);
}
}
if (next_fetch) {
@@ -938,6 +940,7 @@ otx_ep_droq_read_packet(struct otx_ep_device *otx_ep,
last_buf = droq_pkt;
} else {
otx_ep_err("no buf\n");
+ assert(0);
}
pkt_len += cpy_len;
@@ -953,16 +956,7 @@ otx_ep_droq_read_packet(struct otx_ep_device *otx_ep,
droq_pkt->l3_len = hdr_lens.l3_len;
droq_pkt->l4_len = hdr_lens.l4_len;
- if (droq_pkt->nb_segs > 1 &&
- !(otx_ep->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER)) {
- rte_pktmbuf_free(droq_pkt);
- goto oq_read_fail;
- }
-
return droq_pkt;
-
-oq_read_fail:
- return NULL;
}
static inline uint32_t
@@ -992,6 +986,7 @@ otx_ep_recv_pkts(void *rx_queue,
struct rte_mbuf *oq_pkt;
uint32_t pkts = 0;
+ uint32_t valid_pkts = 0;
uint32_t new_pkts = 0;
int next_fetch;
@@ -1019,14 +1014,15 @@ otx_ep_recv_pkts(void *rx_queue,
"last_pkt_count %" PRIu64 "new_pkts %d.\n",
droq->pkts_pending, droq->last_pkt_count,
new_pkts);
- droq->pkts_pending -= pkts;
droq->stats.rx_err++;
- goto finish;
+ continue;
+ } else {
+ rx_pkts[valid_pkts] = oq_pkt;
+ valid_pkts++;
+ /* Stats */
+ droq->stats.pkts_received++;
+ droq->stats.bytes_received += oq_pkt->pkt_len;
}
- rx_pkts[pkts] = oq_pkt;
- /* Stats */
- droq->stats.pkts_received++;
- droq->stats.bytes_received += oq_pkt->pkt_len;
}
droq->pkts_pending -= pkts;
@@ -1053,6 +1049,5 @@ otx_ep_recv_pkts(void *rx_queue,
rte_write32(0, droq->pkts_credit_reg);
}
-finish:
- return pkts;
+ return valid_pkts;
}
diff --git a/drivers/net/octeon_ep/otx_ep_vf.c b/drivers/net/octeon_ep/otx_ep_vf.c
index 96366b2a7f..4f3538146b 100644
--- a/drivers/net/octeon_ep/otx_ep_vf.c
+++ b/drivers/net/octeon_ep/otx_ep_vf.c
@@ -12,10 +12,11 @@
#include "otx_ep_vf.h"
-static void
+static int
otx_ep_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)
{
volatile uint64_t reg_val = 0ull;
+ int loop = OTX_EP_BUSY_LOOP_COUNT;
/* Select ES, RO, NS, RDSIZE,DPTR Format#0 for IQs
* IS_64B is by default enabled.
@@ -33,8 +34,11 @@ otx_ep_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)
do {
reg_val = rte_read64(otx_ep->hw_addr +
OTX_EP_R_IN_CONTROL(q_no));
- } while (!(reg_val & OTX_EP_R_IN_CTL_IDLE));
+ } while (!(reg_val & OTX_EP_R_IN_CTL_IDLE) && loop--);
+ if (loop < 0)
+ return -EIO;
}
+ return 0;
}
static void
@@ -60,13 +64,18 @@ otx_ep_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)
otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_CONTROL(q_no));
}
-static void
+static int
otx_ep_setup_global_input_regs(struct otx_ep_device *otx_ep)
{
uint64_t q_no = 0ull;
+ int ret = 0;
- for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
- otx_ep_setup_global_iq_reg(otx_ep, q_no);
+ for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++) {
+ ret = otx_ep_setup_global_iq_reg(otx_ep, q_no);
+ if (ret)
+ return ret;
+ }
+ return 0;
}
static void
@@ -78,18 +87,24 @@ otx_ep_setup_global_output_regs(struct otx_ep_device *otx_ep)
otx_ep_setup_global_oq_reg(otx_ep, q_no);
}
-static void
+static int
otx_ep_setup_device_regs(struct otx_ep_device *otx_ep)
{
- otx_ep_setup_global_input_regs(otx_ep);
+ int ret;
+
+ ret = otx_ep_setup_global_input_regs(otx_ep);
+ if (ret)
+ return ret;
otx_ep_setup_global_output_regs(otx_ep);
+ return 0;
}
-static void
+static int
otx_ep_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
{
struct otx_ep_instr_queue *iq = otx_ep->instr_queue[iq_no];
volatile uint64_t reg_val = 0ull;
+ int loop = OTX_EP_BUSY_LOOP_COUNT;
reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(iq_no));
@@ -100,7 +115,9 @@ otx_ep_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
do {
reg_val = rte_read64(otx_ep->hw_addr +
OTX_EP_R_IN_CONTROL(iq_no));
- } while (!(reg_val & OTX_EP_R_IN_CTL_IDLE));
+ } while (!(reg_val & OTX_EP_R_IN_CTL_IDLE) && loop--);
+ if (loop < 0)
+ return -EIO;
}
/* Write the start of the input queue's ring and its size */
@@ -120,10 +137,13 @@ otx_ep_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
otx_ep_dbg("InstQ[%d]:dbell reg @ 0x%p inst_cnt_reg @ 0x%p\n",
iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
+ loop = OTX_EP_BUSY_LOOP_COUNT;
do {
reg_val = rte_read32(iq->inst_cnt_reg);
rte_write32(reg_val, iq->inst_cnt_reg);
- } while (reg_val != 0);
+ } while ((reg_val != 0) && loop--);
+ if (loop < 0)
+ return -EIO;
/* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR
* to raise
@@ -133,13 +153,15 @@ otx_ep_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
*/
otx_ep_write64(OTX_EP_CLEAR_IN_INT_LVLS, otx_ep->hw_addr,
OTX_EP_R_IN_INT_LEVELS(iq_no));
+ return 0;
}
-static void
+static int
otx_ep_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
{
volatile uint64_t reg_val = 0ull;
uint64_t oq_ctl = 0ull;
+ int loop = OTX_EP_BUSY_LOOP_COUNT;
struct otx_ep_droq *droq = otx_ep->droq[oq_no];
@@ -150,10 +172,12 @@ otx_ep_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CONTROL(oq_no));
- while (!(reg_val & OTX_EP_R_OUT_CTL_IDLE)) {
+ while (!(reg_val & OTX_EP_R_OUT_CTL_IDLE) && loop--) {
reg_val = rte_read64(otx_ep->hw_addr +
OTX_EP_R_OUT_CONTROL(oq_no));
}
+ if (loop < 0)
+ return -EIO;
otx_ep_write64(droq->desc_ring_dma, otx_ep->hw_addr,
OTX_EP_R_OUT_SLIST_BADDR(oq_no));
@@ -180,11 +204,14 @@ otx_ep_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
OTX_EP_R_OUT_INT_LEVELS(oq_no));
/* Clear the OQ doorbell */
+ loop = OTX_EP_BUSY_LOOP_COUNT;
rte_write32(OTX_EP_CLEAR_SLIST_DBELL, droq->pkts_credit_reg);
- while ((rte_read32(droq->pkts_credit_reg) != 0ull)) {
+ while ((rte_read32(droq->pkts_credit_reg) != 0ull) && loop--) {
rte_write32(OTX_EP_CLEAR_SLIST_DBELL, droq->pkts_credit_reg);
rte_delay_ms(1);
}
+ if (loop < 0)
+ return -EIO;
otx_ep_dbg("OTX_EP_R[%d]_credit:%x\n", oq_no,
rte_read32(droq->pkts_credit_reg));
@@ -195,18 +222,22 @@ otx_ep_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
otx_ep_dbg("OTX_EP_R[%d]_sent: %x\n", oq_no,
rte_read32(droq->pkts_sent_reg));
- while (((rte_read32(droq->pkts_sent_reg)) != 0ull)) {
+ loop = OTX_EP_BUSY_LOOP_COUNT;
+ while (((rte_read32(droq->pkts_sent_reg)) != 0ull) && loop--) {
reg_val = rte_read32(droq->pkts_sent_reg);
rte_write32((uint32_t)reg_val, droq->pkts_sent_reg);
rte_delay_ms(1);
}
+ if (loop < 0)
+ return -EIO;
+ return 0;
}
static int
otx_ep_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
{
- uint64_t loop = OTX_EP_BUSY_LOOP_COUNT;
- uint64_t reg_val = 0ull;
+ volatile uint64_t reg_val = 0ull;
+ int loop = OTX_EP_BUSY_LOOP_COUNT;
/* Resetting doorbells during IQ enabling also to handle abrupt
* guest reboot. IQ reset does not clear the doorbells.
@@ -219,7 +250,7 @@ otx_ep_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
rte_delay_ms(1);
}
- if (loop == 0) {
+ if (loop < 0) {
otx_ep_err("dbell reset failed\n");
return -EIO;
}
@@ -238,8 +269,8 @@ otx_ep_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
static int
otx_ep_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)
{
- uint64_t reg_val = 0ull;
- uint64_t loop = OTX_EP_BUSY_LOOP_COUNT;
+ volatile uint64_t reg_val = 0ull;
+ int loop = OTX_EP_BUSY_LOOP_COUNT;
/* Resetting doorbells during IQ enabling also to handle abrupt
* guest reboot. IQ reset does not clear the doorbells.
@@ -250,7 +281,7 @@ otx_ep_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)
OTX_EP_R_OUT_SLIST_DBELL(q_no))) != 0ull) && loop--) {
rte_delay_ms(1);
}
- if (loop == 0) {
+ if (loop < 0) {
otx_ep_err("dbell reset failed\n");
return -EIO;
}
--
2.31.1
next prev parent reply other threads:[~2023-04-04 14:19 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-04 14:18 [PATCH v1 0/9] extend octeon ep driver functionality Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 1/9] net/octeon_ep: support cnf95n and cnf95o SoC Sathesh Edara
2023-04-05 14:25 ` [PATCH v2 00/10] extend octeon ep driver functionality Sathesh Edara
2023-04-05 14:25 ` [PATCH v2 01/10] net/octeon_ep: support cnf95n and cnf95o SoC Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 00/11] extend octeon ep driver functionality Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 01/11] net/octeon_ep: support cnf95n and cnf95o SoC Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 02/11] net/octeon_ep: support CNX10K series SoC Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 03/11] net/octeon_ep: support error propagation Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 04/11] net/octeon_ep: support IQ/OQ reset Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 05/11] devtools: add acronym in dictionary for commit checks Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 06/11] net/octeon_ep: support ISM Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 07/11] net/octeon_ep: flush pending DMA operations Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 08/11] net/octeon_ep: update queue size checks Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 09/11] net/octeon_ep: support mailbox between VF and PF Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 10/11] net/octeon_ep: set watermark for output queues Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 11/11] net/octeon_ep: set secondary process dev ops Sathesh Edara
2023-04-05 14:25 ` [PATCH v2 02/10] net/octeon_ep: support CNX10K series SoC Sathesh Edara
2023-04-05 14:25 ` [PATCH v2 03/10] net/octeon_ep: support error propagation Sathesh Edara
2023-04-05 14:25 ` [PATCH v2 04/10] net/octeon_ep: support IQ/OQ reset Sathesh Edara
2023-04-05 14:25 ` [PATCH v2 05/10] net/octeon_ep: support ISM Sathesh Edara
2023-04-21 4:56 ` Jerin Jacob
2023-04-05 14:25 ` [PATCH v2 06/10] net/octeon_ep: fix DMA incompletion Sathesh Edara
2023-04-21 4:51 ` Jerin Jacob
2023-04-05 14:25 ` [PATCH v2 07/10] net/octeon_ep: update queue size checks Sathesh Edara
2023-04-05 14:25 ` [PATCH v2 08/10] net/octeon_ep: support Mailbox between VF and PF Sathesh Edara
2023-04-21 5:00 ` Jerin Jacob
2023-04-05 14:25 ` [PATCH v2 09/10] net/octeon_ep: set watermark for output queues Sathesh Edara
2023-04-05 14:25 ` [PATCH v2 10/10] net/octeon_ep: set secondary process dev ops Sathesh Edara
2023-04-21 5:03 ` Jerin Jacob
2023-04-24 12:55 ` [PATCH v3 00/11] extend octeon ep driver functionality Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 01/11] net/octeon_ep: support cnf95n and cnf95o SoC Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 02/11] net/octeon_ep: support CNX10K series SoC Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 03/11] net/octeon_ep: support error propagation Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 04/11] net/octeon_ep: support IQ/OQ reset Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 05/11] devtools: add acronym in dictionary for commit checks Sathesh Edara
2023-05-03 7:16 ` Jerin Jacob
2023-04-24 12:55 ` [PATCH v3 06/11] net/octeon_ep: support ISM Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 07/11] net/octeon_ep: flush pending DMA operations Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 08/11] net/octeon_ep: update queue size checks Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 09/11] net/octeon_ep: support mailbox between VF and PF Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 10/11] net/octeon_ep: set watermark for output queues Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 11/11] net/octeon_ep: set secondary process dev ops Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 2/9] net/octeon_ep: support CNX10K series SoC Sathesh Edara
2023-04-04 14:18 ` Sathesh Edara [this message]
2023-04-04 14:18 ` [PATCH v1 4/9] net/octeon_ep: support IQ/OQ reset Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 5/9] net/octeon_ep: support ISM Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 6/9] net/octeon_ep: fix DMA incompletion Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 7/9] net/octeon_ep: update queue size checks Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 8/9] net/octeon_ep: support Mailbox between VF and PF Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 9/9] net/octeon_ep: set watermark for output queues Sathesh Edara
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