From: Sathesh Edara <sedara@marvell.com>
To: <sburla@marvell.com>, <jerinj@marvell.com>, <sedara@marvell.com>,
"Radha Mohan Chintakuntla" <radhac@marvell.com>,
Veerasenareddy Burru <vburru@marvell.com>
Cc: <dev@dpdk.org>
Subject: [PATCH v2 04/10] net/octeon_ep: support IQ/OQ reset
Date: Wed, 5 Apr 2023 07:25:30 -0700 [thread overview]
Message-ID: <20230405142537.1899973-5-sedara@marvell.com> (raw)
In-Reply-To: <20230405142537.1899973-1-sedara@marvell.com>
This patch adds input and output queue reset
functionality, also receive queue interrupt
enable and disable functionality.
Signed-off-by: Sathesh Edara <sedara@marvell.com>
---
drivers/net/octeon_ep/otx2_ep_vf.c | 193 +++++++++++++++++++++++++-
drivers/net/octeon_ep/otx2_ep_vf.h | 61 ++++++--
drivers/net/octeon_ep/otx_ep_common.h | 5 +-
3 files changed, 244 insertions(+), 15 deletions(-)
diff --git a/drivers/net/octeon_ep/otx2_ep_vf.c b/drivers/net/octeon_ep/otx2_ep_vf.c
index 3ffc7275c7..3e4895862b 100644
--- a/drivers/net/octeon_ep/otx2_ep_vf.c
+++ b/drivers/net/octeon_ep/otx2_ep_vf.c
@@ -9,6 +9,117 @@
#include "otx_ep_common.h"
#include "otx2_ep_vf.h"
+static int otx2_vf_enable_rxq_intr(struct otx_ep_device *otx_epvf,
+ uint16_t q_no);
+
+static int
+otx2_vf_reset_iq(struct otx_ep_device *otx_ep, int q_no)
+{
+ int loop = SDP_VF_BUSY_LOOP_COUNT;
+ volatile uint64_t d64 = 0ull;
+
+ /* There is no RST for a ring.
+ * Clear all registers one by one after disabling the ring
+ */
+
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_BADDR(q_no));
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_RSIZE(q_no));
+
+ d64 = 0xFFFFFFFF; /* ~0ull */
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));
+ d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));
+
+ while ((d64 != 0) && loop--) {
+ rte_delay_ms(1);
+ d64 = otx2_read64(otx_ep->hw_addr +
+ SDP_VF_R_IN_INSTR_DBELL(q_no));
+ }
+ if (loop < 0) {
+ otx_ep_err("%s: doorbell init retry limit exceeded.\n", __func__);
+ return -EIO;
+ }
+
+ loop = SDP_VF_BUSY_LOOP_COUNT;
+ do {
+ d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CNTS(q_no));
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_CNTS(q_no));
+ rte_delay_ms(1);
+ } while ((d64 & ~SDP_VF_R_IN_CNTS_OUT_INT) != 0 && loop--);
+ if (loop < 0) {
+ otx_ep_err("%s: in_cnts init retry limit exceeded.\n", __func__);
+ return -EIO;
+ }
+
+ d64 = 0ull;
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INT_LEVELS(q_no));
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_PKT_CNT(q_no));
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_BYTE_CNT(q_no));
+
+ return 0;
+}
+
+static int
+otx2_vf_reset_oq(struct otx_ep_device *otx_ep, int q_no)
+{
+ int loop = SDP_VF_BUSY_LOOP_COUNT;
+ volatile uint64_t d64 = 0ull;
+
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
+
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_BADDR(q_no));
+
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_RSIZE(q_no));
+
+ d64 = 0xFFFFFFFF;
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));
+ d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));
+ while ((d64 != 0) && loop--) {
+ rte_delay_ms(1);
+ d64 = otx2_read64(otx_ep->hw_addr +
+ SDP_VF_R_OUT_SLIST_DBELL(q_no));
+ }
+ if (loop < 0) {
+ otx_ep_err("%s: doorbell init retry limit exceeded.\n", __func__);
+ return -EIO;
+ }
+
+ if (otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CNTS(q_no))
+ & SDP_VF_R_OUT_CNTS_OUT_INT) {
+ /*
+ * The OUT_INT bit is set. This interrupt must be enabled in
+ * order to clear the interrupt. Interrupts are disabled
+ * at the end of this function.
+ */
+ union out_int_lvl_t out_int_lvl;
+
+ out_int_lvl.d64 = otx2_read64(otx_ep->hw_addr +
+ SDP_VF_R_OUT_INT_LEVELS(q_no));
+ out_int_lvl.s.time_cnt_en = 1;
+ out_int_lvl.s.cnt = 0;
+ otx2_write64(out_int_lvl.d64, otx_ep->hw_addr +
+ SDP_VF_R_OUT_INT_LEVELS(q_no));
+ }
+
+ loop = SDP_VF_BUSY_LOOP_COUNT;
+ do {
+ d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
+ rte_delay_ms(1);
+ } while ((d64 & ~SDP_VF_R_OUT_CNTS_IN_INT) != 0 && loop--);
+ if (loop < 0) {
+ otx_ep_err("%s: out_cnts init retry limit exceeded.\n", __func__);
+ return -EIO;
+ }
+
+ d64 = 0ull;
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_INT_LEVELS(q_no));
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_PKT_CNT(q_no));
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_BYTE_CNT(q_no));
+
+ return 0;
+}
+
static void
otx2_vf_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)
{
@@ -49,24 +160,63 @@ otx2_vf_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)
oct_ep_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
}
+static int
+otx2_vf_reset_input_queues(struct otx_ep_device *otx_ep)
+{
+ uint32_t q_no = 0;
+ int ret = 0;
+
+ for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) {
+ ret = otx2_vf_reset_iq(otx_ep, q_no);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+static int
+otx2_vf_reset_output_queues(struct otx_ep_device *otx_ep)
+{
+ uint64_t q_no = 0ull;
+ int ret = 0;
+
+ for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) {
+ ret = otx2_vf_reset_oq(otx_ep, q_no);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
static int
otx2_vf_setup_global_input_regs(struct otx_ep_device *otx_ep)
{
uint64_t q_no = 0ull;
+ int ret = 0;
+
+ ret = otx2_vf_reset_input_queues(otx_ep);
+ if (ret)
+ return ret;
for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
otx2_vf_setup_global_iq_reg(otx_ep, q_no);
- return 0;
+ return ret;
}
static int
otx2_vf_setup_global_output_regs(struct otx_ep_device *otx_ep)
{
uint32_t q_no;
+ int ret = 0;
+ ret = otx2_vf_reset_output_queues(otx_ep);
+ if (ret)
+ return ret;
for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
otx2_vf_setup_global_oq_reg(otx_ep, q_no);
- return 0;
+ return ret;
}
static int
@@ -181,8 +331,8 @@ otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
rte_write64(OTX_EP_CLEAR_SDP_OUT_PKT_CNT, (uint8_t *)otx_ep->hw_addr +
SDP_VF_R_OUT_PKT_CNT(oq_no));
- loop = OTX_EP_BUSY_LOOP_COUNT;
/* Clear the OQ doorbell */
+ loop = OTX_EP_BUSY_LOOP_COUNT;
rte_write32(OTX_EP_CLEAR_SLIST_DBELL, droq->pkts_credit_reg);
while ((rte_read32(droq->pkts_credit_reg) != 0ull) && loop--) {
rte_write32(OTX_EP_CLEAR_SLIST_DBELL, droq->pkts_credit_reg);
@@ -344,6 +494,40 @@ otx2_ep_get_defconf(struct otx_ep_device *otx_ep_dev __rte_unused)
return default_conf;
}
+static int otx2_vf_enable_rxq_intr(struct otx_ep_device *otx_epvf,
+ uint16_t q_no)
+{
+ union out_int_lvl_t out_int_lvl;
+ union out_cnts_t out_cnts;
+
+ out_int_lvl.d64 = otx2_read64(otx_epvf->hw_addr +
+ SDP_VF_R_OUT_INT_LEVELS(q_no));
+ out_int_lvl.s.time_cnt_en = 1;
+ out_int_lvl.s.cnt = 0;
+ otx2_write64(out_int_lvl.d64, otx_epvf->hw_addr +
+ SDP_VF_R_OUT_INT_LEVELS(q_no));
+ out_cnts.d64 = 0;
+ out_cnts.s.resend = 1;
+ otx2_write64(out_cnts.d64, otx_epvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
+ return 0;
+}
+
+static int otx2_vf_disable_rxq_intr(struct otx_ep_device *otx_epvf,
+ uint16_t q_no)
+{
+ union out_int_lvl_t out_int_lvl;
+
+ /* Disable the interrupt for this queue */
+ out_int_lvl.d64 = otx2_read64(otx_epvf->hw_addr +
+ SDP_VF_R_OUT_INT_LEVELS(q_no));
+ out_int_lvl.s.time_cnt_en = 0;
+ out_int_lvl.s.cnt = 0;
+ otx2_write64(out_int_lvl.d64, otx_epvf->hw_addr +
+ SDP_VF_R_OUT_INT_LEVELS(q_no));
+
+ return 0;
+}
+
int
otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)
{
@@ -381,5 +565,8 @@ otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)
otx_ep->fn_list.enable_oq = otx2_vf_enable_oq;
otx_ep->fn_list.disable_oq = otx2_vf_disable_oq;
+ otx_ep->fn_list.enable_rxq_intr = otx2_vf_enable_rxq_intr;
+ otx_ep->fn_list.disable_rxq_intr = otx2_vf_disable_rxq_intr;
+
return 0;
}
diff --git a/drivers/net/octeon_ep/otx2_ep_vf.h b/drivers/net/octeon_ep/otx2_ep_vf.h
index 8f00acd737..36c0b25dea 100644
--- a/drivers/net/octeon_ep/otx2_ep_vf.h
+++ b/drivers/net/octeon_ep/otx2_ep_vf.h
@@ -14,17 +14,20 @@
#define SDP_VF_BUSY_LOOP_COUNT (10000)
/* SDP VF OQ Masks */
-#define SDP_VF_R_OUT_CTL_IDLE (1ull << 40)
-#define SDP_VF_R_OUT_CTL_ES_I (1ull << 34)
-#define SDP_VF_R_OUT_CTL_NSR_I (1ull << 33)
-#define SDP_VF_R_OUT_CTL_ROR_I (1ull << 32)
-#define SDP_VF_R_OUT_CTL_ES_D (1ull << 30)
-#define SDP_VF_R_OUT_CTL_NSR_D (1ull << 29)
-#define SDP_VF_R_OUT_CTL_ROR_D (1ull << 28)
-#define SDP_VF_R_OUT_CTL_ES_P (1ull << 26)
-#define SDP_VF_R_OUT_CTL_NSR_P (1ull << 25)
-#define SDP_VF_R_OUT_CTL_ROR_P (1ull << 24)
-#define SDP_VF_R_OUT_CTL_IMODE (1ull << 23)
+#define SDP_VF_R_OUT_CTL_IDLE (0x1ull << 40)
+#define SDP_VF_R_OUT_CTL_ES_I (0x1ull << 34)
+#define SDP_VF_R_OUT_CTL_NSR_I (0x1ull << 33)
+#define SDP_VF_R_OUT_CTL_ROR_I (0x1ull << 32)
+#define SDP_VF_R_OUT_CTL_ES_D (0x1ull << 30)
+#define SDP_VF_R_OUT_CTL_NSR_D (0x1ull << 29)
+#define SDP_VF_R_OUT_CTL_ROR_D (0x1ull << 28)
+#define SDP_VF_R_OUT_CTL_ES_P (0x1ull << 26)
+#define SDP_VF_R_OUT_CTL_NSR_P (0x1ull << 25)
+#define SDP_VF_R_OUT_CTL_ROR_P (0x1ull << 24)
+#define SDP_VF_R_OUT_CTL_IMODE (0x1ull << 23)
+#define SDP_VF_R_OUT_CNTS_OUT_INT (0x1ull << 62)
+#define SDP_VF_R_OUT_CNTS_IN_INT (0x1ull << 61)
+#define SDP_VF_R_IN_CNTS_OUT_INT (0x1ull << 62)
/* SDP VF Register definitions */
#define SDP_VF_RING_OFFSET (0x1ull << 17)
@@ -140,4 +143,40 @@ struct otx2_ep_instr_64B {
uint64_t exhdr[4];
};
+union out_int_lvl_t {
+ uint64_t d64;
+ struct {
+ uint64_t cnt:32;
+ uint64_t timet:22;
+ uint64_t max_len:7;
+ uint64_t max_len_en:1;
+ uint64_t time_cnt_en:1;
+ uint64_t bmode:1;
+ } s;
+};
+
+union out_cnts_t {
+ uint64_t d64;
+ struct {
+ uint64_t cnt:32;
+ uint64_t timer:22;
+ uint64_t rsvd:5;
+ uint64_t resend:1;
+ uint64_t mbox_int:1;
+ uint64_t in_int:1;
+ uint64_t out_int:1;
+ uint64_t send_ism:1;
+ } s;
+};
+
+#define OTX2_EP_64B_INSTR_SIZE (sizeof(otx2_ep_instr_64B))
+
+#define NIX_MAX_HW_FRS 9212
+#define NIX_MAX_VTAG_INS 2
+#define NIX_MAX_VTAG_ACT_SIZE (4 * NIX_MAX_VTAG_INS)
+#define NIX_MAX_FRS \
+ (NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)
+
+#define CN93XX_INTR_R_OUT_INT (1ULL << 62)
+#define CN93XX_INTR_R_IN_INT (1ULL << 61)
#endif /*_OTX2_EP_VF_H_ */
diff --git a/drivers/net/octeon_ep/otx_ep_common.h b/drivers/net/octeon_ep/otx_ep_common.h
index 479bb1a1a0..a3260d5243 100644
--- a/drivers/net/octeon_ep/otx_ep_common.h
+++ b/drivers/net/octeon_ep/otx_ep_common.h
@@ -408,6 +408,9 @@ struct otx_ep_fn_list {
int (*enable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no);
void (*disable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no);
+
+ int (*enable_rxq_intr)(struct otx_ep_device *otx_epvf, uint16_t q_no);
+ int (*disable_rxq_intr)(struct otx_ep_device *otx_epvf, uint16_t q_no);
};
/* OTX_EP EP VF device data structure */
@@ -498,7 +501,7 @@ struct otx_ep_buf_free_info {
struct otx_ep_gather g;
};
-#define OTX_EP_MAX_PKT_SZ 64000U
+#define OTX_EP_MAX_PKT_SZ 65498U
#define OTX_EP_MAX_MAC_ADDRS 1
#define OTX_EP_SG_ALIGN 8
#define OTX_EP_CLEAR_ISIZE_BSIZE 0x7FFFFFULL
--
2.31.1
next prev parent reply other threads:[~2023-04-05 14:26 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-04 14:18 [PATCH v1 0/9] extend octeon ep driver functionality Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 1/9] net/octeon_ep: support cnf95n and cnf95o SoC Sathesh Edara
2023-04-05 14:25 ` [PATCH v2 00/10] extend octeon ep driver functionality Sathesh Edara
2023-04-05 14:25 ` [PATCH v2 01/10] net/octeon_ep: support cnf95n and cnf95o SoC Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 00/11] extend octeon ep driver functionality Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 01/11] net/octeon_ep: support cnf95n and cnf95o SoC Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 02/11] net/octeon_ep: support CNX10K series SoC Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 03/11] net/octeon_ep: support error propagation Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 04/11] net/octeon_ep: support IQ/OQ reset Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 05/11] devtools: add acronym in dictionary for commit checks Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 06/11] net/octeon_ep: support ISM Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 07/11] net/octeon_ep: flush pending DMA operations Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 08/11] net/octeon_ep: update queue size checks Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 09/11] net/octeon_ep: support mailbox between VF and PF Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 10/11] net/octeon_ep: set watermark for output queues Sathesh Edara
2023-04-24 12:28 ` [PATCH v3 11/11] net/octeon_ep: set secondary process dev ops Sathesh Edara
2023-04-05 14:25 ` [PATCH v2 02/10] net/octeon_ep: support CNX10K series SoC Sathesh Edara
2023-04-05 14:25 ` [PATCH v2 03/10] net/octeon_ep: support error propagation Sathesh Edara
2023-04-05 14:25 ` Sathesh Edara [this message]
2023-04-05 14:25 ` [PATCH v2 05/10] net/octeon_ep: support ISM Sathesh Edara
2023-04-21 4:56 ` Jerin Jacob
2023-04-05 14:25 ` [PATCH v2 06/10] net/octeon_ep: fix DMA incompletion Sathesh Edara
2023-04-21 4:51 ` Jerin Jacob
2023-04-05 14:25 ` [PATCH v2 07/10] net/octeon_ep: update queue size checks Sathesh Edara
2023-04-05 14:25 ` [PATCH v2 08/10] net/octeon_ep: support Mailbox between VF and PF Sathesh Edara
2023-04-21 5:00 ` Jerin Jacob
2023-04-05 14:25 ` [PATCH v2 09/10] net/octeon_ep: set watermark for output queues Sathesh Edara
2023-04-05 14:25 ` [PATCH v2 10/10] net/octeon_ep: set secondary process dev ops Sathesh Edara
2023-04-21 5:03 ` Jerin Jacob
2023-04-24 12:55 ` [PATCH v3 00/11] extend octeon ep driver functionality Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 01/11] net/octeon_ep: support cnf95n and cnf95o SoC Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 02/11] net/octeon_ep: support CNX10K series SoC Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 03/11] net/octeon_ep: support error propagation Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 04/11] net/octeon_ep: support IQ/OQ reset Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 05/11] devtools: add acronym in dictionary for commit checks Sathesh Edara
2023-05-03 7:16 ` Jerin Jacob
2023-04-24 12:55 ` [PATCH v3 06/11] net/octeon_ep: support ISM Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 07/11] net/octeon_ep: flush pending DMA operations Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 08/11] net/octeon_ep: update queue size checks Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 09/11] net/octeon_ep: support mailbox between VF and PF Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 10/11] net/octeon_ep: set watermark for output queues Sathesh Edara
2023-04-24 12:55 ` [PATCH v3 11/11] net/octeon_ep: set secondary process dev ops Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 2/9] net/octeon_ep: support CNX10K series SoC Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 3/9] net/octeon_ep: support error propagation Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 4/9] net/octeon_ep: support IQ/OQ reset Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 5/9] net/octeon_ep: support ISM Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 6/9] net/octeon_ep: fix DMA incompletion Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 7/9] net/octeon_ep: update queue size checks Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 8/9] net/octeon_ep: support Mailbox between VF and PF Sathesh Edara
2023-04-04 14:18 ` [PATCH v1 9/9] net/octeon_ep: set watermark for output queues Sathesh Edara
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for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).