From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9D139428E9; Sat, 8 Apr 2023 04:30:12 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9BDD442D4B; Sat, 8 Apr 2023 04:29:37 +0200 (CEST) Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) by mails.dpdk.org (Postfix) with ESMTP id 4C0DC42C54; Sat, 8 Apr 2023 04:29:35 +0200 (CEST) Received: from kwepemi500017.china.huawei.com (unknown [172.30.72.55]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4PtfLZ4pDHzKrVk; Sat, 8 Apr 2023 10:28:54 +0800 (CST) Received: from localhost.localdomain (10.28.79.22) by kwepemi500017.china.huawei.com (7.221.188.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Sat, 8 Apr 2023 10:29:33 +0800 From: Dongdong Liu To: , , , CC: , , , Yisen Zhuang Subject: [PATCH 6/7] net/hns3: add LLRS FEC mode support for 200G ports Date: Sat, 8 Apr 2023 10:27:38 +0800 Message-ID: <20230408022740.14522-7-liudongdong3@huawei.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20230408022740.14522-1-liudongdong3@huawei.com> References: <20230408022740.14522-1-liudongdong3@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.28.79.22] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemi500017.china.huawei.com (7.221.188.110) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Jie Hai This patch supports the query and configuration of LLRS FEC mode. Signed-off-by: Jie Hai Signed-off-by: Dongdong Liu --- drivers/net/hns3/hns3_cmd.c | 1 + drivers/net/hns3/hns3_cmd.h | 2 ++ drivers/net/hns3/hns3_ethdev.c | 21 ++++++++++++--------- 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c index bdfc85f934..a574191ba9 100644 --- a/drivers/net/hns3/hns3_cmd.c +++ b/drivers/net/hns3/hns3_cmd.c @@ -637,6 +637,7 @@ hns3_firmware_compat_config(struct hns3_hw *hw, bool is_init) if (is_init) { hns3_set_bit(compat, HNS3_LINK_EVENT_REPORT_EN_B, 1); hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0); + hns3_set_bit(compat, HNS3_LLRS_FEC_EN_B, 1); if (hns3_dev_get_support(hw, COPPER)) hns3_set_bit(compat, HNS3_FIRMWARE_PHY_DRIVER_EN_B, 1); } diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index eb394c9dec..a86f5116e4 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -665,6 +665,7 @@ enum hns3_promisc_type { #define HNS3_LINK_EVENT_REPORT_EN_B 0 #define HNS3_NCSI_ERROR_REPORT_EN_B 1 #define HNS3_FIRMWARE_PHY_DRIVER_EN_B 2 +#define HNS3_LLRS_FEC_EN_B 5 struct hns3_firmware_compat_cmd { uint32_t compat; uint8_t rsv[20]; @@ -806,6 +807,7 @@ struct hns3_sfp_info_cmd { #define HNS3_MAC_FEC_OFF 0 #define HNS3_MAC_FEC_BASER 1 #define HNS3_MAC_FEC_RS 2 +#define HNS3_MAC_FEC_LLRS 3 /* Configure FEC mode, opcode:0x031A */ struct hns3_config_fec_cmd { diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 80cdcc83bf..8f998947c6 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -47,11 +47,6 @@ #define HNS3_RESET_WAIT_MS 100 #define HNS3_RESET_WAIT_CNT 200 -/* FEC mode order defined in HNS3 hardware */ -#define HNS3_HW_FEC_MODE_NOFEC 0 -#define HNS3_HW_FEC_MODE_BASER 1 -#define HNS3_HW_FEC_MODE_RS 2 - enum hns3_evt_cause { HNS3_VECTOR0_EVENT_RST, HNS3_VECTOR0_EVENT_MBX, @@ -91,7 +86,8 @@ static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = { RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, { RTE_ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | - RTE_ETH_FEC_MODE_CAPA_MASK(RS) } + RTE_ETH_FEC_MODE_CAPA_MASK(RS) | + RTE_ETH_FEC_MODE_CAPA_MASK(LLRS) } }; static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns, @@ -6059,15 +6055,18 @@ hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa) * to be converted. */ switch (resp->active_fec) { - case HNS3_HW_FEC_MODE_NOFEC: + case HNS3_MAC_FEC_OFF: tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); break; - case HNS3_HW_FEC_MODE_BASER: + case HNS3_MAC_FEC_BASER: tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); break; - case HNS3_HW_FEC_MODE_RS: + case HNS3_MAC_FEC_RS: tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS); break; + case HNS3_MAC_FEC_LLRS: + tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(LLRS); + break; default: tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); break; @@ -6108,6 +6107,10 @@ hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode) hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS); break; + case RTE_ETH_FEC_MODE_CAPA_MASK(LLRS): + hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, + HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_LLRS); + break; case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO): hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1); break; -- 2.22.0