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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 13:27:56.7673 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e02e2fdb-ab9b-4c20-525d-08db3c22e4cb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7645 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding support for AMD CDX devices Signed-off-by: Nipun Gupta --- config/arm/arm64_cdx_linux_gcc | 17 +++++++++++++++++ config/arm/meson.build | 14 ++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 config/arm/arm64_cdx_linux_gcc diff --git a/config/arm/arm64_cdx_linux_gcc b/config/arm/arm64_cdx_linux_gcc new file mode 100644 index 0000000000..8e6d619dae --- /dev/null +++ b/config/arm/arm64_cdx_linux_gcc @@ -0,0 +1,17 @@ +[binaries] +c = ['ccache', 'aarch64-linux-gnu-gcc'] +cpp = ['ccache', 'aarch64-linux-gnu-g++'] +ar = 'aarch64-linux-gnu-ar' +as = 'aarch64-linux-gnu-as' +strip = 'aarch64-linux-gnu-strip' +pkgconfig = 'aarch64-linux-gnu-pkg-config' +pcap-config = '' + +[host_machine] +system = 'linux' +cpu_family = 'aarch64' +cpu = 'armv8-a' +endian = 'little' + +[properties] +platform = 'cdx' diff --git a/config/arm/meson.build b/config/arm/meson.build index 5213434ca4..39b8929534 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -305,6 +305,18 @@ soc_bluefield = { 'numa': false } +soc_cdx = { + 'description': 'AMD CDX', + 'implementer': '0x41', + 'part_number': '0xd42', + 'flags': [ + ['RTE_MACHINE', '"cdx"'], + ['RTE_MAX_LCORE', 16], + ['RTE_MAX_NUMA_NODES', 1] + ], + 'numa': false +} + soc_centriq2400 = { 'description': 'Qualcomm Centriq 2400', 'implementer': '0x51', @@ -463,6 +475,7 @@ generic_aarch32: Generic un-optimized build for armv8 aarch32 execution mode. armada: Marvell ARMADA bluefield: NVIDIA BlueField bluefield3: NVIDIA BlueField-3 +cdx: AMD CDX centriq2400: Qualcomm Centriq 2400 cn9k: Marvell OCTEON 9 cn10k: Marvell OCTEON 10 @@ -490,6 +503,7 @@ socs = { 'armada': soc_armada, 'bluefield': soc_bluefield, 'bluefield3': soc_bluefield3, + 'cdx': soc_cdx, 'centriq2400': soc_centriq2400, 'cn9k': soc_cn9k, 'cn10k' : soc_cn10k, -- 2.17.1