From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 67C7A429DB; Mon, 24 Apr 2023 14:55:33 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E8175410DE; Mon, 24 Apr 2023 14:55:32 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 6EF0D410D0 for ; Mon, 24 Apr 2023 14:55:31 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33O7WYOA028418 for ; Mon, 24 Apr 2023 05:55:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=0zIrGu02qlw+oyZcrPANTO1y+6s4v+eZG0xfg6kBfbQ=; b=H4mdSCF8NBlqQlUofafJPctRT+nJDZlATA5dTb3/IreVWSSOAWpBV8vzxh5dTdUXLl40 5grm/7A9UoJF393yr9mk9vZu8rhfaQKVd9FqZrIQAEoiBTP3sHO8LUdJCy7EcRrYgvT7 0raq782bHwPfWQIddIxXk1AaF2CqQ+1yOrFE8bam460KT3BCyOi8p0SoqB+/JJu1zgdW t83gnjmpm5+pkJWRo8fHiGhB0CyzgJiXkdPYAzwStzsg2qwOusLadEHNctyLuboWBI9T TMcCPdK5/sRJoqG8JGWj7zCfX7cyWsht5/ibymC2uGQgEK7Jwwlkr3ElEXs0l3B1LRhG bA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3q5nfb125w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 24 Apr 2023 05:55:30 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 24 Apr 2023 05:55:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Mon, 24 Apr 2023 05:55:28 -0700 Received: from localhost.marvell.com (unknown [10.106.27.249]) by maili.marvell.com (Postfix) with ESMTP id 94FF63F70A0; Mon, 24 Apr 2023 05:55:28 -0700 (PDT) From: Sathesh Edara To: , , , "Radha Mohan Chintakuntla" , Veerasenareddy Burru CC: Subject: [PATCH v3 08/11] net/octeon_ep: update queue size checks Date: Mon, 24 Apr 2023 05:55:08 -0700 Message-ID: <20230424125512.40013-9-sedara@marvell.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230424125512.40013-1-sedara@marvell.com> References: <20230405142537.1899973-1-sedara@marvell.com> <20230424125512.40013-1-sedara@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: ox-Mwbxf2HrkUGrMGCOJWmtM3iV3QWnT X-Proofpoint-GUID: ox-Mwbxf2HrkUGrMGCOJWmtM3iV3QWnT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-24_07,2023-04-21_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Updates the output queue size checks to ensure that queue is larger than backpressure watermark. Add setting of default queue sizes to the minimum so that applications like testpmd can be started without explicit queue size arguments. Signed-off-by: Sathesh Edara --- drivers/net/octeon_ep/otx_ep_common.h | 9 +++++++-- drivers/net/octeon_ep/otx_ep_ethdev.c | 12 ++++++++++-- drivers/net/octeon_ep/otx_ep_rxtx.h | 4 ++-- 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/net/octeon_ep/otx_ep_common.h b/drivers/net/octeon_ep/otx_ep_common.h index 444136923f..3582f3087b 100644 --- a/drivers/net/octeon_ep/otx_ep_common.h +++ b/drivers/net/octeon_ep/otx_ep_common.h @@ -11,8 +11,13 @@ #define OTX_EP_MAX_RINGS_PER_VF (8) #define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF #define OTX_EP_64BYTE_INSTR (64) -#define OTX_EP_MIN_IQ_DESCRIPTORS (128) -#define OTX_EP_MIN_OQ_DESCRIPTORS (128) +/* + * Backpressure for SDP is configured on Octeon, and the minimum queue sizes + * must be much larger than the backpressure watermark configured in the Octeon + * SDP driver. IQ and OQ backpressure configurations are separate. + */ +#define OTX_EP_MIN_IQ_DESCRIPTORS (2048) +#define OTX_EP_MIN_OQ_DESCRIPTORS (2048) #define OTX_EP_MAX_IQ_DESCRIPTORS (8192) #define OTX_EP_MAX_OQ_DESCRIPTORS (8192) #define OTX_EP_OQ_BUF_SIZE (2048) diff --git a/drivers/net/octeon_ep/otx_ep_ethdev.c b/drivers/net/octeon_ep/otx_ep_ethdev.c index 30a7a450fb..0f710b1ffa 100644 --- a/drivers/net/octeon_ep/otx_ep_ethdev.c +++ b/drivers/net/octeon_ep/otx_ep_ethdev.c @@ -48,6 +48,9 @@ otx_ep_dev_info_get(struct rte_eth_dev *eth_dev, devinfo->rx_desc_lim = otx_ep_rx_desc_lim; devinfo->tx_desc_lim = otx_ep_tx_desc_lim; + devinfo->default_rxportconf.ring_size = OTX_EP_MIN_OQ_DESCRIPTORS; + devinfo->default_txportconf.ring_size = OTX_EP_MIN_IQ_DESCRIPTORS; + return 0; } @@ -274,8 +277,8 @@ otx_ep_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t q_no, return -EINVAL; } if (num_rx_descs < (SDP_GBL_WMARK * 8)) { - otx_ep_err("Invalid rx desc number should at least be greater than 8xwmark %u\n", - num_rx_descs); + otx_ep_err("Invalid rx desc number(%u) should at least be greater than 8xwmark %u\n", + num_rx_descs, (SDP_GBL_WMARK * 8)); return -EINVAL; } @@ -357,6 +360,11 @@ otx_ep_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t q_no, num_tx_descs); return -EINVAL; } + if (num_tx_descs < (SDP_GBL_WMARK * 8)) { + otx_ep_err("Invalid tx desc number(%u) should at least be greater than 8*wmark(%u)\n", + num_tx_descs, (SDP_GBL_WMARK * 8)); + return -EINVAL; + } retval = otx_ep_setup_iqs(otx_epvf, q_no, num_tx_descs, socket_id); diff --git a/drivers/net/octeon_ep/otx_ep_rxtx.h b/drivers/net/octeon_ep/otx_ep_rxtx.h index 1527d350b5..7012888100 100644 --- a/drivers/net/octeon_ep/otx_ep_rxtx.h +++ b/drivers/net/octeon_ep/otx_ep_rxtx.h @@ -7,8 +7,8 @@ #include -#define OTX_EP_RXD_ALIGN 1 -#define OTX_EP_TXD_ALIGN 1 +#define OTX_EP_RXD_ALIGN 2 +#define OTX_EP_TXD_ALIGN 2 #define OTX_EP_IQ_SEND_FAILED (-1) #define OTX_EP_IQ_SEND_SUCCESS (0) -- 2.31.1